JP2007110112A - 炭素含有膜エッチング方法及びこれを利用した半導体素子の製造方法 - Google Patents
炭素含有膜エッチング方法及びこれを利用した半導体素子の製造方法 Download PDFInfo
- Publication number
- JP2007110112A JP2007110112A JP2006272137A JP2006272137A JP2007110112A JP 2007110112 A JP2007110112 A JP 2007110112A JP 2006272137 A JP2006272137 A JP 2006272137A JP 2006272137 A JP2006272137 A JP 2006272137A JP 2007110112 A JP2007110112 A JP 2007110112A
- Authority
- JP
- Japan
- Prior art keywords
- carbon
- containing film
- gas
- etching
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005530 etching Methods 0.000 title claims abstract description 135
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 title claims abstract description 105
- 229910052799 carbon Inorganic materials 0.000 title claims abstract description 105
- 238000000034 method Methods 0.000 title claims abstract description 78
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 23
- 239000007789 gas Substances 0.000 claims abstract description 97
- 239000000203 mixture Substances 0.000 claims abstract 3
- 239000010410 layer Substances 0.000 claims description 95
- 229920000642 polymer Polymers 0.000 claims description 23
- 239000011229 interlayer Substances 0.000 claims description 20
- 239000006227 byproduct Substances 0.000 claims description 18
- 239000011261 inert gas Substances 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 238000001020 plasma etching Methods 0.000 claims description 6
- 229910003902 SiCl 4 Inorganic materials 0.000 claims description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 230000000149 penetrating effect Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 238000000059 patterning Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 description 16
- 238000001878 scanning electron micrograph Methods 0.000 description 11
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 239000012528 membrane Substances 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 2
- 230000004907 flux Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- -1 N 2 Substances 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 101100107923 Vitis labrusca AMAT gene Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910003481 amorphous carbon Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02115—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material being carbon, e.g. alpha-C, diamond or hydrogen doped carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3146—Carbon layers, e.g. diamond-like layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】炭素含有膜上に炭素含有膜の上面を一部露出させるマスクパターンを形成し、マスクパターンをエッチングマスクとして利用して、O2、及びSi含有ガスからなる混合ガスのプラズマによって炭素含有膜を異方性エッチングする炭素含有膜エッチング方法である。これにより、高密度セルアレイ領域で互いに隣接した2個のコンタクトホールの間隔が数十nmまたはそれ以下のレベルに小さくなっても、コンタクトホールが互いに良好に分離して隣接した単位セル間の短絡が防止される。
【選択図】図2C
Description
110 層間絶縁膜
110a 層間絶縁膜パターン
120 炭素含有膜
120a 炭素含有膜パターン
120h ホール
130 キャッピング層
130a、320、420 キャッピング層パターン
140 有機反射防止膜
140a 有機反射防止膜パターン
150 フォトレジストパターン
160 混合ガス
170、330、430 ポリマー副産物層
310、410 ACLパターン
B 底部
Claims (23)
- 炭素含有膜上に前記炭素含有膜の上面を一部露出させるマスクパターンを形成する段階と、
前記マスクパターンをエッチングマスクとして利用して、O2、及びSi含有ガスからなる混合ガスのプラズマによって前記炭素含有膜を異方性エッチングして、炭素含有膜パターンを形成する段階とを含むことを特徴とする炭素含有膜エッチング方法。 - 前記Si含有ガスは、SiF4、SiCl4、SiH4、及びSiClxFy(x+y=4)からなる群から選択されるいずれか一つ、またはその組み合わせからなることを特徴とする請求項1に記載の炭素含有膜エッチング方法。
- 前記混合ガスは、その総量を基準に50〜95体積%のO2と、5〜50体積%のSi含有ガスからなることを特徴とする請求項1に記載の炭素含有膜エッチング方法。
- 前記混合ガスは、N2及び非活性ガスのうちから選択される少なくとも一つの物質をさらに含むことを特徴とする請求項1に記載の炭素含有膜エッチング方法。
- 前記混合ガスは、前記混合ガスの総量を基準に20〜95体積%のO2と、前記混合ガスの総量を基準に5〜50体積%のSi含有ガスと、前記O2の総量を基準に0〜100体積%のN2と、前記O2の総量を基準に0〜50体積%の非活性ガスとからなること(但し、N2及び非活性ガスの含有量が同時に0ではない)を特徴とする請求項4に記載の炭素含有膜エッチング方法。
- 前記非活性ガスは、Ar、He、Xe、及びKrからなる群から選択されるいずれか一つであることを特徴とする請求項4に記載の炭素含有膜エッチング方法。
- 前記混合ガスは、CxFy(x,yはそれぞれ定数)系ガスをさらに含むことを特徴とする請求項1に記載の炭素含有膜エッチング方法。
- 前記CxFy系ガスは、前記混合ガスの総量を基準に10体積%未満の量で含まれることを特徴とする請求項7に記載の炭素含有膜エッチング方法。
- 前記炭素含有膜は、ACL、SiLK、NCP、及びAHMからなる群から選択されるいずれか一つからなることを特徴とする請求項1に記載の炭素含有膜エッチング方法。
- 前記炭素含有膜パターンが形成された後、前記炭素含有膜パターン及び前記マスクパターン上に存在するポリマー副産物を、CF4、Cl2、またはこれらの組み合わせからなるガスを利用するプラズマエッチング工程によって除去する段階をさらに含むことを特徴とする請求項1に記載の炭素含有膜エッチング方法。
- 前記マスクパターンは、シリコン酸化膜、シリコン酸化窒化膜、Si、SiGe、またはこれらの組み合わせからなることを特徴とする請求項1に記載の炭素含有膜エッチング方法。
- 半導体基板上に層間絶縁膜を形成する段階と、
前記層間絶縁膜上に炭素含有膜を形成する段階と、
前記炭素含有膜上にキャッピング層を形成する段階と、
フォトリソグラフィ工程を利用して前記キャッピング層をパターニングして、前記炭素含有膜の上面を一部露出させるキャッピング層パターンを形成する段階と、
前記キャッピング層パターンをエッチングマスクとして、O2、及びSi含有ガスからなる混合ガスのプラズマによって、前記炭素含有膜を異方性エッチングして炭素含有膜パターンを形成する段階と、
前記炭素含有膜パターンをエッチングマスクとして、前記層間絶縁膜を異方性エッチングして、前記層間絶縁膜を貫通するコンタクトホールを形成する段階とを含むことを特徴とする半導体素子の製造方法。 - 前記Si含有ガスは、SiF4、SiCl4、SiH4、及びSiClxFy(x+y=4)からなる群から選択されるいずれか一つ、またはその組み合わせからなることを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記混合ガスは、その総量を基準に50〜95体積%のO2と、5〜50体積%のSi含有ガスとからなることを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記混合ガスは、N2及び非活性ガスのうちから選択される少なくとも一つの物質をさらに含むことを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記混合ガスは、前記混合ガスの総量を基準に20〜95体積%のO2と、前記混合ガスの総量を基準に5〜50体積%のSi含有ガスと、前記O2の総量を基準に0〜100体積%のN2と、前記O2の総量を基準に0〜50体積%の非活性ガスとからなること(但し、N2及び非活性ガスの含有量が同時に0ではない)を特徴とする請求項15に記載の半導体素子の製造方法。
- 前記非活性ガスは、Ar、He、Xe、及びKrからなる群から選択されるいずれか一つであることを特徴とする請求項15に記載の半導体素子の製造方法。
- 前記混合ガスは、CxFy系ガスをさらに含むことを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記CxFy(x,yはそれぞれ定数)系ガスは、前記混合ガスの総量を基準に10体積%未満の量で含まれることを特徴とする請求項18に記載の半導体素子の製造方法。
- 前記炭素含有膜は、ACL、SiLK、NCP、及びAHMからなる群から選択されるいずれか一つからなることを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記炭素含有膜パターンが形成された後、前記炭素含有膜パターン及びキャッピング層パターン上に存在するポリマー副産物を、CF4、Cl2、またはこれらの組み合わせからなるガスを利用するプラズマエッチング工程によって除去する段階をさらに含むことを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記キャッピング層は、シリコン酸化膜、シリコン酸化窒化膜、Si、SiGe、またはこれらの組み合わせからなることを特徴とする請求項12に記載の半導体素子の製造方法。
- 前記キャッピング層は、SiON、PE酸化膜、TEOS、ALDによって形成された酸化膜、Si、SiGe、またはこれらの組み合わせからなることを特徴とする請求項12に記載の半導体素子の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050096164A KR100780944B1 (ko) | 2005-10-12 | 2005-10-12 | 탄소함유막 식각 방법 및 이를 이용한 반도체 소자의 제조방법 |
KR10-2005-0096164 | 2005-10-12 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007110112A true JP2007110112A (ja) | 2007-04-26 |
JP2007110112A5 JP2007110112A5 (ja) | 2009-11-19 |
JP5122106B2 JP5122106B2 (ja) | 2013-01-16 |
Family
ID=37911496
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006272137A Active JP5122106B2 (ja) | 2005-10-12 | 2006-10-03 | 炭素含有膜エッチング方法及びこれを利用した半導体素子の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7494934B2 (ja) |
JP (1) | JP5122106B2 (ja) |
KR (1) | KR100780944B1 (ja) |
CN (1) | CN100570830C (ja) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010016213A (ja) * | 2008-07-04 | 2010-01-21 | Tokyo Electron Ltd | プラズマエッチング方法、制御プログラム及びコンピュータ記憶媒体 |
KR20150079931A (ko) * | 2012-11-01 | 2015-07-08 | 어플라이드 머티어리얼스, 인코포레이티드 | 낮은-k 유전 필름을 패턴화시키는 방법 |
JP2017059822A (ja) * | 2015-09-18 | 2017-03-23 | セントラル硝子株式会社 | ドライエッチング方法及びドライエッチング剤 |
KR20180124705A (ko) * | 2017-05-11 | 2018-11-21 | 주성엔지니어링(주) | 기판 처리 방법 및 그를 이용한 유기 발광 소자 제조 방법 |
KR20190017227A (ko) * | 2017-08-10 | 2019-02-20 | 삼성전자주식회사 | 집적회로 소자의 제조 방법 |
JP2019186572A (ja) * | 2016-03-28 | 2019-10-24 | 株式会社日立ハイテクノロジーズ | プラズマ処理方法 |
JP2021515988A (ja) * | 2018-03-16 | 2021-06-24 | ラム リサーチ コーポレーションLam Research Corporation | 誘電体における高アスペクト比フィーチャのプラズマエッチング化学物質 |
Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7517804B2 (en) * | 2006-08-31 | 2009-04-14 | Micron Technologies, Inc. | Selective etch chemistries for forming high aspect ratio features and associated structures |
TWI455203B (zh) * | 2007-05-03 | 2014-10-01 | Lam Res Corp | 開孔之硬遮罩及藉由開孔之硬遮罩施行之蝕刻輪廓控制 |
KR100950553B1 (ko) * | 2007-08-31 | 2010-03-30 | 주식회사 하이닉스반도체 | 반도체 소자의 콘택 형성 방법 |
JP5226296B2 (ja) * | 2007-12-27 | 2013-07-03 | 東京エレクトロン株式会社 | プラズマエッチング方法、プラズマエッチング装置、制御プログラム及びコンピュータ記憶媒体 |
US8133819B2 (en) * | 2008-02-21 | 2012-03-13 | Applied Materials, Inc. | Plasma etching carbonaceous layers with sulfur-based etchants |
JP2010041028A (ja) | 2008-07-11 | 2010-02-18 | Tokyo Electron Ltd | 基板処理方法 |
JP2010283213A (ja) * | 2009-06-05 | 2010-12-16 | Tokyo Electron Ltd | 基板処理方法 |
TW201304162A (zh) * | 2011-05-17 | 2013-01-16 | Intevac Inc | 製作太陽能電池背側點接觸的方法 |
US8916054B2 (en) * | 2011-10-26 | 2014-12-23 | International Business Machines Corporation | High fidelity patterning employing a fluorohydrocarbon-containing polymer |
TWI497586B (zh) * | 2011-10-31 | 2015-08-21 | Hitachi High Tech Corp | Plasma etching method |
JP5932599B2 (ja) | 2011-10-31 | 2016-06-08 | 株式会社日立ハイテクノロジーズ | プラズマエッチング方法 |
KR20130107628A (ko) | 2012-03-22 | 2013-10-02 | 삼성디스플레이 주식회사 | 트렌치 형성 방법, 금속 배선 형성 방법, 및 박막 트랜지스터 표시판의 제조 방법 |
CN103377991B (zh) * | 2012-04-18 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 沟槽的形成方法 |
CN104425221B (zh) * | 2013-08-28 | 2017-12-01 | 中芯国际集成电路制造(上海)有限公司 | 图形化方法 |
CN104425222B (zh) * | 2013-08-28 | 2018-09-07 | 中芯国际集成电路制造(上海)有限公司 | 图形化方法 |
KR102362065B1 (ko) | 2015-05-27 | 2022-02-14 | 삼성전자주식회사 | 반도체 소자의 제조 방법 |
KR20180097763A (ko) * | 2016-01-20 | 2018-08-31 | 어플라이드 머티어리얼스, 인코포레이티드 | 측방향 하드마스크 리세스 감소를 위한 하이브리드 탄소 하드마스크 |
US10978302B2 (en) | 2017-11-29 | 2021-04-13 | Lam Research Corporation | Method of improving deposition induced CD imbalance using spatially selective ashing of carbon based film |
CN108538712B (zh) * | 2018-04-25 | 2020-08-25 | 武汉新芯集成电路制造有限公司 | 接触孔的制造方法 |
CN111446204B (zh) * | 2019-01-17 | 2024-02-06 | 中芯国际集成电路制造(上海)有限公司 | 半导体结构及其形成方法 |
US12037686B2 (en) | 2019-06-24 | 2024-07-16 | Lam Research Corporation | Selective carbon deposition |
JP7321059B2 (ja) * | 2019-11-06 | 2023-08-04 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0590224A (ja) * | 1991-01-22 | 1993-04-09 | Toshiba Corp | 半導体装置の製造方法 |
JPH10144676A (ja) * | 1996-11-14 | 1998-05-29 | Tokyo Electron Ltd | 半導体素子の製造方法 |
JP2002093778A (ja) * | 2000-09-11 | 2002-03-29 | Toshiba Corp | 有機膜のエッチング方法およびこれを用いた半導体装置の製造方法 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5240554A (en) * | 1991-01-22 | 1993-08-31 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
JP3282292B2 (ja) * | 1993-06-07 | 2002-05-13 | ソニー株式会社 | ドライエッチング方法 |
US5545579A (en) * | 1995-04-04 | 1996-08-13 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a sub-quarter micrometer channel field effect transistor having elevated source/drain areas and lightly doped drains |
JP2002510878A (ja) | 1998-04-02 | 2002-04-09 | アプライド マテリアルズ インコーポレイテッド | 低k誘電体をエッチングする方法 |
US6703265B2 (en) * | 2000-08-02 | 2004-03-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP3526438B2 (ja) * | 2000-09-07 | 2004-05-17 | 株式会社日立製作所 | 試料のエッチング処理方法 |
US6835663B2 (en) | 2002-06-28 | 2004-12-28 | Infineon Technologies Ag | Hardmask of amorphous carbon-hydrogen (a-C:H) layers with tunable etch resistivity |
KR20040003652A (ko) * | 2002-07-03 | 2004-01-13 | 주식회사 하이닉스반도체 | 반도체 소자의 게이트 형성 방법 |
US20040079726A1 (en) | 2002-07-03 | 2004-04-29 | Advanced Micro Devices, Inc. | Method of using an amorphous carbon layer for improved reticle fabrication |
JP2004031892A (ja) | 2002-12-27 | 2004-01-29 | Fujitsu Ltd | アモルファスカーボンを用いた半導体装置の製造方法 |
KR100510558B1 (ko) * | 2003-12-13 | 2005-08-26 | 삼성전자주식회사 | 패턴 형성 방법 |
US7115524B2 (en) * | 2004-05-17 | 2006-10-03 | Micron Technology, Inc. | Methods of processing a semiconductor substrate |
-
2005
- 2005-10-12 KR KR1020050096164A patent/KR100780944B1/ko active IP Right Grant
-
2006
- 2006-08-29 US US11/512,026 patent/US7494934B2/en active Active
- 2006-10-03 JP JP2006272137A patent/JP5122106B2/ja active Active
- 2006-10-11 CN CNB2006101321471A patent/CN100570830C/zh active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0590224A (ja) * | 1991-01-22 | 1993-04-09 | Toshiba Corp | 半導体装置の製造方法 |
JPH10144676A (ja) * | 1996-11-14 | 1998-05-29 | Tokyo Electron Ltd | 半導体素子の製造方法 |
JP2002093778A (ja) * | 2000-09-11 | 2002-03-29 | Toshiba Corp | 有機膜のエッチング方法およびこれを用いた半導体装置の製造方法 |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010016213A (ja) * | 2008-07-04 | 2010-01-21 | Tokyo Electron Ltd | プラズマエッチング方法、制御プログラム及びコンピュータ記憶媒体 |
KR20150079931A (ko) * | 2012-11-01 | 2015-07-08 | 어플라이드 머티어리얼스, 인코포레이티드 | 낮은-k 유전 필름을 패턴화시키는 방법 |
KR102164568B1 (ko) * | 2012-11-01 | 2020-10-12 | 어플라이드 머티어리얼스, 인코포레이티드 | 낮은-k 유전 필름을 패턴화시키는 방법 |
JP2017059822A (ja) * | 2015-09-18 | 2017-03-23 | セントラル硝子株式会社 | ドライエッチング方法及びドライエッチング剤 |
JP2019186572A (ja) * | 2016-03-28 | 2019-10-24 | 株式会社日立ハイテクノロジーズ | プラズマ処理方法 |
KR20180124705A (ko) * | 2017-05-11 | 2018-11-21 | 주성엔지니어링(주) | 기판 처리 방법 및 그를 이용한 유기 발광 소자 제조 방법 |
KR102582762B1 (ko) | 2017-05-11 | 2023-09-25 | 주성엔지니어링(주) | 기판 처리 방법 및 그를 이용한 유기 발광 소자 제조 방법 |
KR20190017227A (ko) * | 2017-08-10 | 2019-02-20 | 삼성전자주식회사 | 집적회로 소자의 제조 방법 |
KR102372892B1 (ko) | 2017-08-10 | 2022-03-10 | 삼성전자주식회사 | 집적회로 소자의 제조 방법 |
JP2021515988A (ja) * | 2018-03-16 | 2021-06-24 | ラム リサーチ コーポレーションLam Research Corporation | 誘電体における高アスペクト比フィーチャのプラズマエッチング化学物質 |
JP7366918B2 (ja) | 2018-03-16 | 2023-10-23 | ラム リサーチ コーポレーション | 誘電体における高アスペクト比フィーチャのプラズマエッチング化学物質 |
US12119243B2 (en) | 2018-03-16 | 2024-10-15 | Lam Research Corporation | Plasma etching chemistries of high aspect ratio features in dielectrics |
Also Published As
Publication number | Publication date |
---|---|
CN1956154A (zh) | 2007-05-02 |
KR20070040633A (ko) | 2007-04-17 |
KR100780944B1 (ko) | 2007-12-03 |
JP5122106B2 (ja) | 2013-01-16 |
CN100570830C (zh) | 2009-12-16 |
US20070082483A1 (en) | 2007-04-12 |
US7494934B2 (en) | 2009-02-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5122106B2 (ja) | 炭素含有膜エッチング方法及びこれを利用した半導体素子の製造方法 | |
US9508560B1 (en) | SiARC removal with plasma etch and fluorinated wet chemical solution combination | |
US7291550B2 (en) | Method to form a contact hole | |
US6800550B2 (en) | Method for forming t-shaped conductive wires of semiconductor device utilizing notching phenomenon | |
US8106519B2 (en) | Methods for pitch reduction | |
JP2004096117A (ja) | 自己整合型接点用の突出スペーサ | |
US20090068842A1 (en) | Method for forming micropatterns in semiconductor device | |
US8089153B2 (en) | Method for eliminating loading effect using a via plug | |
WO2022100070A1 (zh) | 光刻胶的处理方法及自对准双图案化方法 | |
JP2008218999A (ja) | 半導体装置の製造方法 | |
US20080160759A1 (en) | Method for fabricating landing plug contact in semiconductor device | |
TW200824002A (en) | Method for fabricating semiconductor device | |
JP2007096214A (ja) | 半導体装置の製造方法 | |
KR100851922B1 (ko) | 반도체 소자의 제조방법 | |
US10224414B2 (en) | Method for providing a low-k spacer | |
US20120122310A1 (en) | Method of manufacturing semiconductor device | |
JP2005327873A (ja) | 半導体装置及びその製造方法 | |
KR101037690B1 (ko) | 반도체소자의 제조방법 | |
JP2005136097A (ja) | 半導体装置の製造方法 | |
KR20070000719A (ko) | 반도체 소자의 비트라인콘택 형성방법 | |
KR100764452B1 (ko) | 반도체 소자 및 이의 제조 방법 | |
KR20080061165A (ko) | 반도체 소자의 콘택홀 형성 방법 | |
JP5276824B2 (ja) | 半導体装置の製造方法 | |
JP4768732B2 (ja) | 半導体装置及びその製造方法、ドライエッチング方法、配線材料の作製方法、並びにエッチング装置 | |
TWI419201B (zh) | 圖案化的方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091001 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20091001 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100922 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110921 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110927 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20111227 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20120403 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120801 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20120808 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120925 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20121024 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20151102 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 Ref document number: 5122106 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |