JP5009626B2 - ピラー構造セルのフラッシュメモリ技術 - Google Patents
ピラー構造セルのフラッシュメモリ技術 Download PDFInfo
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
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- H10B—ELECTRONIC MEMORY DEVICES
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
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- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
Description
Claims (24)
- 半導体基板の少なくとも一部を横切って形成された消去可能で再プログラム可能な不揮発性メモリセルのアレイであって、
自己整合した積層からなる素子が離間して配置された二次元アレイであって、基板表面上のゲート誘電層と、前記ゲート誘電層上の導電性フローティングゲートと、前記フローティングゲート上のインターゲート誘電層と、前記インターゲート誘電層上の導電性コントロールゲートとを備える二次元アレイと、
個々の積層間および個々の積層の周囲で、前記基板内に形成された絶縁用のトレンチと、
前記コントロールゲートと接触して積層面を横切って延び、隣接する積層のフローティングゲート間の空間内に突出した少なくとも第1のセットの長い導体と、
前記積層面を横切って延び、かつ隣接する積層のフローティングゲート間の空間内に延びることによって、前記導体が隣接する積層のフローティングゲート間にシールドを設ける第2のセットの長い導体と、を備え、
前記第1および第2のセットの長い導体が互いに垂直に前記アレイを横切って配列されることによって、前記第1および第2のセットの長い導体が全ての積層面の周囲にシールドを設けるアレイ。 - 請求項1記載のアレイにおいて、
前記積層に隣接したトレンチ内に形成された選択トランジスタをさらに備えるアレイ。 - 請求項1記載のアレイにおいて、
前記積層に隣接したトレンチ内に形成され、トンネル誘電体層を貫いて結合される前記トレンチ内にゲートを備える選択トランジスタをさらに備えるアレイ。 - 半導体基板の少なくとも一部を横切って形成された消去可能で再プログラム可能な不揮発性メモリセルのアレイであって、
前記基板を横切って平面図で見て方形に形成され、かつ4隅が互いに自己整合した素子から個々に形成された二次元アレイのピラーであって、基板表面上のゲート誘電層と、前記ゲート誘電層上の導電性フローティングゲートと、前記フローティングゲート上のインターゲート誘電層と、前記インターゲート誘電層上の導電性コントロールゲートとを備える二次元アレイのピラーと、
個々のピラー間、個々のピラーの周囲、および個々のピラー間の空間の下で、前記基板内に形成されたトレンチと、
前記コントロールゲートの上を通って前記コントロールゲートと接触し、前記アレイを横切って第1の方向に延び、かつ隣接するピラーのフローティングゲート間の空間内に第1の方向に延びる第1の複数の並列ゲート導体と、
前記アレイを横切って第2の方向に延びる第2の複数の並列ゲート導体であって、第1の方向と第2の方向とは互いに直交し、前記第1の複数の並列ゲート導体から絶縁され、隣接するピラーのフローティングゲート間の空間内に延び、第2の方向にある少なくとも幾つかのピラー間のトレンチ内に位置するトランジスタの選択ゲートと結合される第2の複数の並列ゲート導体と、
少なくとも幾つかのピラーとは別の第2の方向にあるピラー間のトレンチ内のソースおよびドレイン・イオン注入部と、
前記ソースおよびドレイン・イオン注入部と接触して前記トレンチ内を第1の方向に延びる複数の並列ビットライン導体と、を備え、
前記ソースおよびドレイン・イオン注入部の1つを含まないトレンチの側壁の近傍で上方に、かつ前記トレンチ間に位置するフローティングゲート内で加速するように電子をプログラムするための経路を前記基板内に設けるアレイ。 - 請求項4記載のアレイにおいて、
前記ソースおよびドレイン・イオン注入部が第1の方向に複数のピラーを横切って延在するアレイ。 - 請求項5記載のアレイにおいて、
前記延在するソースおよびドレイン・イオン注入部と接触して前記トレンチ内を第1の方向に延びる複数の並列ビットライン導体をさらに備えるアレイ。 - 請求項4記載のアレイにおいて、
前記選択ゲートは、前記第2の複数の並列ゲート導体と一体に形成されるアレイ。 - 請求項4記載のアレイにおいて、
前記選択ゲートは、間に挟まれたトンネル誘電体層を貫いて前記第2の複数の並列ゲート導体と結合されるアレイ。 - 請求項4記載のアレイにおいて、
前記インターゲート誘電層は、二酸化シリコン層によって両側が囲まれた窒化シリコン層を含むアレイ。 - 請求項4記載のアレイにおいて、
前記ピラーの側壁は、基板表面と垂直方向に向いているアレイ。 - 請求項4記載のアレイにおいて、
前記トレンチの深さは、400〜800ナノメータ内にあるアレイ。 - 請求項4記載のアレイにおいて、
前記選択ゲートと前記トレンチの底部との間の前記トレンチ内に、第2の複数の並列ゲート導体と前記フローティングゲートの縁部との間の誘電体よりも厚い誘電体をさらに備えるアレイ。 - 半導体基板の少なくとも一部を横切って形成された消去可能で再プログラム可能な不揮発性メモリセルのアレイであって、
前記基板を横切って平面図で見て方形に形成され、かつ4隅が互いに自己整合した素子から個々に形成された二次元アレイのピラーであって、基板表面上のゲート誘電層と、前記ゲート誘電層上の導電性フローティングゲートと、前記フローティングゲート上のインターゲート誘電層と、前記インターゲート誘電層上の導電性コントロールゲートとを備える二次元アレイのピラーと、
個々のピラー間、個々のピラーの周囲、および個々のピラー間の空間の下で、前記基板内に形成されたトレンチと、
前記コントロールゲートの上を通って前記コントロールゲートと接触し、前記アレイを横切って第1の方向に延び、かつ隣接するピラーのフローティングゲート間の空間内に第1の方向に延びて、シールドを設ける第1の複数の並列ゲート導体と、
前記アレイを横切って第2の方向に延びる第2の複数の並列ゲート導体であって、第1の方向と第2の方向とは互いに直交し、第1の複数の並列ゲート導体から絶縁され、隣接するピラーのフローティングゲート間の空間内に第2の方向に延びて、シールドを設ける第2の複数の並列ゲート導体と、
前記アレイを横切って第2の方向に延びる第1のセットの1つおきのトレンチの底部で隣接するピラー間にある前記基板内のソースおよびドレイン・イオン注入部と、
隣接するピラー間に、また前記アレイを横切って第2の方向に延びる第2のセットの1つおきのトレンチ内に位置する選択ゲートを備える選択トランジスタであって、前記第1および第2のセットの1つおきのトレンチは互いに別個のものであり、前記選択ゲートは隣接するピラー間の空間内に延びる前記第2の複数の並列ゲート導体の一部と結合される選択トランジスタと、を備え、
それによって2つのソースおよびドレイン・イオン注入部と、前記2つのソースおよびドレイン・イオン注入部の間の選択トランジスタとを個々に備えるメモリセルのアレイを第2の方向に設けるアレイ。 - 請求項13記載のアレイにおいて、
前記ソースおよびドレイン・イオン注入部と接触して前記トレンチ内を第1の方向に延びる複数の並列ビットライン導体をさらに備えるアレイ。 - 請求項13記載のアレイにおいて、
前記ソースおよびドレイン・イオン注入部が第1の方向に複数のピラーを横切って延在するアレイ。 - 請求項15記載のアレイにおいて、
前記延在するソースおよびドレイン・イオン注入部と接触して前記トレンチ内を第1の方向に延びる複数の並列ビットライン導体をさらに備えるアレイ。 - 請求項13記載のアレイにおいて、
前記選択ゲートは、前記第2の複数の並列ゲート導体と一体に形成されるアレイ。 - 請求項13記載のアレイにおいて、
前記選択ゲートは、間に挟まれたトンネル誘電体層を貫いて前記第2の複数の並列ゲート導体と結合されるアレイ。 - 半導体基板の少なくとも一部を横切って形成された消去可能で再プログラム可能な不揮発性メモリセルのアレイであって、
基板表面を横切って形成された方形アレイの電荷蓄積素子と、
少なくとも幾つかの電荷蓄積素子間で前記基板内に形成されたトレンチと、
第1の方向にシールドを設けるように、電荷蓄積素子を横切って延び、電荷蓄積素子間で下方に延びる部分を有する長いコントロールゲートと、
第1の方向に垂直な第2の方向にシールドを設けるように、少なくとも幾つかのトレンチ内に位置する選択トランジスタゲートと、
を備えるアレイ。 - 請求項19記載のアレイにおいて、
前記電荷蓄積素子は、導電性フローティングゲートであるアレイ。 - 請求項19記載のアレイにおいて、
前記トンネル誘電体層の厚みは、0.5〜4nmの範囲にあるアレイ。 - 請求項19記載のアレイにおいて、
前記選択トランジスタゲートと前記トレンチの底部との間に、前記コントロールゲートと前記電荷蓄積素子との間の誘電体層よりも厚い誘電体層をさらに備えるアレイ。 - 半導体基板の少なくとも一部を横切って消去可能で再プログラム可能な不揮発性メモリセルのアレイを形成する方法であって、
基板表面の少なくともアレイ部分を横切って第1の誘電材料層を形成するステップと、
前記第1の誘電材料層上に少なくともアレイ部分を横切って第1の導電材料層を形成するステップと、
前記第1の導電材料の層上に第2の誘電材料層を形成するステップと、
前記第2の誘電材料層上に第2の導電材料層を形成するステップと、
前記第1および第2の導電材料層と前記第1および第2の誘電材料層とを貫いて基板表面に第1のセットのチャネルを異方性エッチングして、内部にトレンチを形成するステップであって、前記第1のセットのチャネルおよびトレンチはアレイ部分を横切って第1の方向に延び、かつアレイ部分を横切って第2の方向に離隔され、第1と第2の方向は互いに直交するステップと、
その後、前記第1および第2の導電材料層と前記第1および第2の誘電材料層とを貫いて基板表面に第2のセットのチャネルを異方性エッチングして、内部にトレンチを形成するステップであって、前記第2のセットのチャネルおよびトレンチはアレイ部分を横切って第2の方向に延び、かつアレイ部分を横切って第1の方向に離隔されるステップと、を含み、
それによって前記第1および第2のセットのチャネルとトレンチとによって囲まれたアレイ部分を横切ってアレイのピラーが残され、
その後、前記ピラーの一部として残った第2の導電材料層と接触して前記第2の導電材料層を横切って延び、かつ第1の方向に延びて第2の方向で離隔される第1のセットの導体を形成するステップと、
その後、間に誘電体を設けながら前記第1のセットの導体を横切って延び、かつ第2の方向に延びて第1の方向で離隔される第2のセットの導体を形成するステップと、をさらに含み、
前記第1および第2のセットの導体をそれぞれ形成するステップは、隣接するピラー間のチャネル内に前記導体を延ばし、少なくとも、隣接するピラーのフローティングゲートを第1の方向と第2の方向の双方で互いにシールドする範囲まで延ばすことを含み、
前記第2のセットの導体を形成するステップの前に、第2の方向に沿って少なくとも幾つかのピラー間の位置で前記トレンチにイオンを注入し、それによってソース領域およびドレイン領域を形成するステップをさらに含み、
前記第2のセットの導体を形成するステップは、ソースおよびドレイン領域がまだ形成されていない少なくとも幾つかのピラー間にある第2の方向に沿った位置で、間に誘電体を設けながら前記第2のセットの導体を前記トレンチ内に延ばし、それによって隣接するピラーのフローティングゲートを第2の方向で互いに絶縁させて、選択トランジスタゲートとして役立つようにすることを含む方法。 - 請求項23記載の方法において、
前記第1のセットの導体を形成するステップは、隣接するピラーのフローティングゲート間のチャネル内に前記第1のセットの導体を第1の方向に延ばし、それによって隣接するピラーのフローティングゲートを第1の方向で互いに絶縁させることを含む方法。
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US7049652B2 (en) | 2006-05-23 |
JP2007520876A (ja) | 2007-07-26 |
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US7253055B2 (en) | 2007-08-07 |
TW200541081A (en) | 2005-12-16 |
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