JP2007520876A - ピラー構造セルのフラッシュメモリ技術 - Google Patents
ピラー構造セルのフラッシュメモリ技術 Download PDFInfo
- Publication number
- JP2007520876A JP2007520876A JP2006543889A JP2006543889A JP2007520876A JP 2007520876 A JP2007520876 A JP 2007520876A JP 2006543889 A JP2006543889 A JP 2006543889A JP 2006543889 A JP2006543889 A JP 2006543889A JP 2007520876 A JP2007520876 A JP 2007520876A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- array
- trench
- conductors
- extending
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000015654 memory Effects 0.000 title claims abstract description 194
- 238000005516 engineering process Methods 0.000 title description 19
- 238000007667 floating Methods 0.000 claims abstract description 191
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000004020 conductor Substances 0.000 claims description 56
- 238000003860 storage Methods 0.000 claims description 48
- 238000000034 method Methods 0.000 claims description 37
- 239000007943 implant Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 239000004065 semiconductor Substances 0.000 claims description 10
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 150000002500 ions Chemical class 0.000 claims 11
- 239000003989 dielectric material Substances 0.000 claims 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 62
- 229920005591 polysilicon Polymers 0.000 abstract description 62
- 238000012545 processing Methods 0.000 abstract description 7
- 238000003491 array Methods 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 229
- 238000002347 injection Methods 0.000 description 37
- 239000007924 injection Substances 0.000 description 37
- 229910052751 metal Inorganic materials 0.000 description 32
- 239000002184 metal Substances 0.000 description 32
- 230000008878 coupling Effects 0.000 description 27
- 238000010168 coupling process Methods 0.000 description 27
- 238000005859 coupling reaction Methods 0.000 description 27
- 239000012212 insulator Substances 0.000 description 22
- 230000001965 increasing effect Effects 0.000 description 20
- 238000009792 diffusion process Methods 0.000 description 19
- 239000002784 hot electron Substances 0.000 description 18
- 230000002829 reductive effect Effects 0.000 description 15
- 230000005641 tunneling Effects 0.000 description 15
- 230000005684 electric field Effects 0.000 description 14
- 238000005530 etching Methods 0.000 description 14
- 230000011218 segmentation Effects 0.000 description 13
- 239000000463 material Substances 0.000 description 12
- 230000007246 mechanism Effects 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 238000002513 implantation Methods 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 9
- 230000008901 benefit Effects 0.000 description 8
- 238000000151 deposition Methods 0.000 description 8
- 230000008021 deposition Effects 0.000 description 8
- 230000000694 effects Effects 0.000 description 8
- 229910052681 coesite Inorganic materials 0.000 description 7
- 229910052906 cristobalite Inorganic materials 0.000 description 7
- 238000009413 insulation Methods 0.000 description 7
- 229910052682 stishovite Inorganic materials 0.000 description 7
- 229910052905 tridymite Inorganic materials 0.000 description 7
- 238000012795 verification Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000001459 lithography Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 230000009977 dual effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- 230000002441 reversible effect Effects 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 238000007740 vapor deposition Methods 0.000 description 4
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 230000001419 dependent effect Effects 0.000 description 3
- 230000005055 memory storage Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000012937 correction Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000002427 irreversible effect Effects 0.000 description 2
- 238000007726 management method Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 101001105315 Bacillus subtilis (strain 168) 50S ribosomal protein L17 Proteins 0.000 description 1
- 101100018928 Drosophila melanogaster InR gene Proteins 0.000 description 1
- 241000270295 Serpentes Species 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005421 electrostatic potential Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
- G11C16/0458—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates comprising two or more independent floating gates which store independent data
Abstract
Description
Claims (33)
- 半導体基板の少なくとも一部を横切って形成された消去可能で再プログラム可能な不揮発性メモリセルのアレイにおいて、
前記基板の表面上のゲート誘電層と、前記ゲート誘電層上の導電性フローティングゲートと、前記フローティングゲート上のインターゲート誘電層と、前記インターゲート誘電層上の導電性コントロールゲートとを含む自己整合素子の離間された積層の二次元アレイと、
個々の前記積層の間の周囲および前記基板内に形成された絶縁トレンチと、
前記積層のコントロールゲートと接触し前記積層と交差して延び、隣接する積層のフローティングゲート間の空間内に突出した少なくとも第1のセットの長い導体と、
を備えるアレイ。 - 前記積層と交差し、また隣接する積層の前記フローティングゲート間の空間内に延び、これによって前記導体が前記隣接する積層の前記フローティングゲート間にシールドを設ける第2のセットの長い導体をさらに備える請求項1記載のアレイ。
- 前記第1のセットおよび第2のセットの長い導体が前記アレイを横切って互いに垂直に配列され、これによって前記導体が前記積層の全ての面の周囲にシールドを設ける請求項2記載のアレイ。
- 前記積層に隣接したトレンチ内に形成され、前記空間に突出する前記第1のセットの長い導体の一部の端部から形成されたゲートを前記トレンチ内に含む選択トランジスタをさらに備える請求項1記載のアレイ。
- 前記積層に隣接したトレンチ内に形成され、前記第1のセットの長い導体の一部と結合し、前記空間の間にあるトンネル誘電体を貫いて前記空間内に突出したゲートを前記トレンチ内に含む選択トランジスタをさらに備える請求項1記載のアレイ。
- 半導体基板の少なくとも一部を横切って形成された消去可能で再プログラム可能な不揮発性メモリセルのアレイにおいて、
前記基板を横切って平面図で見て方形に形成され、かつ4隅が互いに自己整合した素子から個々に形成され、前記基板の表面上にゲート誘電層を含み、前記ゲート誘電層上に導電性フローティングゲートを含み、前記フローティングゲート上にインターゲート誘電層を含み、前記インターゲート誘電層上に導電性コントロールゲートを含むピラーの二次元アレイと、
個々の前記ピラーの間に、前記個々のピラーの周囲に、前記ピラー間の空間の下に、および前記基板内に形成されたトレンチと、
前記ピラーの前記コントロールゲートの上を通り、前記ゲートと接触し、前記アレイを横切って第1の方向に延び、隣接するピラーのフローティングゲート間の空間内に前記第1の方向に延びる第1の複数の並列ゲート導体と、
前記アレイを横切って第2の方向に延びる第2の複数の並列ゲート導体であって、前記第1の方向と第2の方向とは互いに直交し、前記第2のゲート導体は前記第1のゲート導体から絶縁され、隣接するピラーのフローティングゲート間の空間内に延び、前記ピラーの前記第2の方向にある少なくとも幾つかの間のトレンチ内に位置するトランジスタの選択ゲートと結合される第2の複数の並列ゲート導体と、
を備えるアレイ。 - 前記ピラーの少なくとも幾つかとは別の前記第2の方向にあるピラーの間の基板トレンチ内にソースおよびドレイン・イオン注入部をさらに備える請求項6記載のアレイ。
- 前記ソースおよびドレイン・イオン注入部と接触して前記第1の方向に前記トレンチ内の前記アレイを横切って延びる複数の並列ビットライン導体をさらに備える請求項7記載のアレイ。
- 前記ソースおよびドレイン・イオン注入部の1つを含まないトレンチの側壁の近傍で電子が上方に、かつ前記トレンチ間に位置するフローティングゲート内に加速するようにプログラムする経路が前記基板内に設けられる請求項7記載のアレイ。
- 前記ソースおよびドレイン・イオン注入部が第1の方向に複数のピラーにわたって延在する請求項7記載のアレイ。
- 前記延在するソースおよびドレイン・イオン注入部と接触し、前記第1の方向に前記トレンチ内の前記アレイと交差して延びる複数の並列ビットライン導体をさらに備える請求項10記載のアレイ。
- 前記選択ゲートは、前記第2のゲート導体と一体に形成される請求項6記載のアレイ。
- 前記選択ゲートは、間に挟まれたトンネル誘電体層を過ぎて前記第2のゲート導体と結合される請求項6記載のアレイ。
- 前記インターゲート誘電層は、二酸化シリコン層によって両側が囲まれた窒化シリコン層を含む請求項6記載のアレイ。
- 前記ピラーの側壁は、基板表面と垂直方向に向いている請求項6記載のアレイ。
- 前記トレンチの深さは、400〜800ナノメータ内である請求項6記載のアレイ。
- 前記選択ゲートと前記トレンチの底部との間および前記トレンチ内に、前記第2の複数のゲート導体と前記フローティングゲートの縁部との間の誘電体よりも厚い誘電体をさらに備える請求項6記載のアレイ。
- 半導体基板の少なくとも一部を横切って形成された消去可能で再プログラム可能な不揮発性メモリセルのアレイにおいて、
前記基板を横切って平面図で見て方形に形成され、かつ4隅が互いに自己整合した素子から個々に形成され、前記基板の表面上にゲート誘電層を含み、前記ゲート誘電層上に導電性フローティングゲートを含み、前記フローティングゲート上にインターゲート誘電層を含み、前記インターゲート誘電層上に導電性コントロールゲートを含むピラーの二次元アレイと、
個々の前記ピラーの間に、前記個々のピラーの周囲に、前記ピラー間の空間の下に、および基板内に形成されたトレンチと、
前記ピラーの前記コントロールゲートの上を通り、前記ゲートと接触し、前記アレイを横切って第1の方向に延び、隣接するピラーのフローティングゲート間の空間内に前記第1の方向に延びる第1の複数の並列ゲート導体と、
前記アレイを横切って第2の方向に延びる第2の複数の並列ゲート導体であって、前記第1の方向と第2の方向とは互いに直交し、前記第2のゲート導体は第1のゲート導体から絶縁され、隣接するピラーのフローティングゲート間の空間内に第2の方向に延びる第2の複数の並列ゲート導体と、
前記基板内にあり、前記アレイを横切って第2の方向に延びる第1のセットの1つおきのトレンチの底部の隣接するピラーの間にあるソースおよびドレイン・イオン注入部と、
隣接するピラーの間に、また前記アレイを横切って第2の方向に延びる第2のセットの1つおきのトレンチ内に位置する選択ゲートを含む選択トランジスタであって、前記第1のセットおよび第2のセットの1つおきのトレンチは互いに別個であり、前記選択ゲートは隣接するピラー間の空間内に延びる前記第2のゲート導体の一部と結合されている選択トランジスタと、を備え、
それによって2つのソースおよびドレイン・イオン注入部と前記層の間の選択トランジスタとを個々に含むメモリセルアレイを第2の方向に備えるアレイ。 - 前記ソースおよびドレイン・イオン注入部と接触して前記第1の方向に前記トレンチ内に前記アレイを横切って延びる複数の並列ビットライン導体をさらに備える請求項18記載のアレイ。
- 前記ソースおよびドレイン・イオン注入部が第1の方向に複数のピラーにわたって延在する請求項18記載のアレイ。
- 前記延在するソースおよびドレイン・イオン注入部と接触し、前記第1の方向に前記トレンチ内の前記アレイと交差して延びる複数の並列ビットライン導体をさらに備える請求項20記載のアレイ。
- 前記選択ゲートは、前記第2のゲート導体と一体に形成される請求項18記載のアレイ。
- 前記選択ゲートは、間に挟まれたトンネル誘電体を過ぎて前記第2のゲート導体と結合される請求項18記載のアレイ。
- 半導体基板の少なくとも一部を横切って形成された消去可能で再プログラム可能な不揮発性メモリセルのアレイにおいて、
前記基板の表面を横切って形成された電荷蓄積素子の方形アレイと、
前記電荷蓄積素子の少なくとも幾つかの間で前記基板内に形成されたトレンチと、
電荷蓄積素子と交差して延び、前記電荷蓄積素子の間に下方に延びる部分を有する長いコントロールゲートと、
前記トレンチの少なくとも幾つかの内部に配置され、間に挟まれたトンネル誘電体層を過ぎて前記下方に延びるコントロールゲートの部分と結合された選択トランジスタゲートと、
を備えるアレイ。 - 前記電荷蓄積素子は、導電性フローティングゲートである請求項24記載のアレイ。
- 前記トンネル誘電体層の厚みは、0.5〜4nmの範囲である請求項24記載のアレイ。
- 前記選択トランジスタゲートと前記トレンチの底部との間に、前記コントロールゲートと前記電荷蓄積素子との間の誘電体層よりも厚い誘電体層をさらに備える請求項24記載のアレイ。
- 半導体基板の少なくとも一部を横切って消去可能で再プログラム可能な不揮発性メモリセルのアレイを形成する方法において、
前記基板の表面の少なくとも前記アレイ部分を横切って第1の誘電体層を形成するステップと、
前記第1の誘電体層の上に少なくとも前記アレイ部分を横切って第1の導電材料の層を形成するステップと、
前記第1の導電材料の層の上に第2の誘電材料の層を形成するステップと、
前記第2の誘電体層の上に第2の導電材料の層を形成するステップと、
前記第1および第2の導電材料の層と前記第1および第2の誘電材料の層とを貫いて前記基板表面内に第1のセットのチャネルを異方性エッチングして内部にトレンチを形成するステップであって、前記第1のセットのチャネルおよびトレンチは前記アレイ部分を横切る1つの方向に延び、かつ前記アレイ部分を横切る第2の方向に離隔され、前記第1と第2の方向は互いに直行しているステップと、
その後、前記第1および第2の導電材料の層と前記第1および第2の誘電材料の層とを貫いて前記基板表面内に第2のセットのチャネルを異方性エッチングして内部にトレンチを形成するステップであって、前記第2のセットのチャネルおよびトレンチは前記アレイ部分を横切る第2の方向に延び、かつ前記アレイ部分を横切る前記第1の方向に離隔されるステップと、
それによって前記第1のセットおよび第2のセットのチャネルおよびトレンチによって囲まれるアレイ部分を横切るピラーのアレイが残されるステップと、
その後、前記ピラーの一部として残る前記第2の導電材料の層を横切って、前記第2の導電材料の層と接触して延びる1つのセットの導体を形成するステップであって、前記1つのセットの導体は前記第1の方向に延び、前記第2の方向で離隔されるステップと、
を含む方法。 - その後、間に誘電体を設けながら前記1つのセットの導体を横切って延びる第2のセットの導体を形成するステップであって、前記第2のセットの導体は前記第2の方向に延び、前記第1の方向で離隔されるステップをさらに含む請求項28記載の方法。
- 前記1つのセットの導体および第2のセットの導体をそれぞれ形成するステップは、隣接するピラー間の前記チャネル内に前記導体を延ばし、少なくとも、隣接するピラーのフローティングゲートを前記第1の方向と第2の方向の双方で互いにシールドする範囲まで延ばすステップを含む請求項29記載の方法。
- 前記第2のセットの導体を形成する前に、前記第2の方向に沿って前記ピラーの少なくとも幾つかの間の位置で前記トレンチにイオンを注入し、それによってソース領域およびドレイン領域を形成するステップをさらに含む請求項29記載の方法。
- 前記第2のセットの導体を形成するステップは、ソースおよびドレイン領域がまだ形成されておらず、前記ピラーの少なくとも幾つかの間にある前記第2の方向に沿った位置で、間に誘電体を設けながら前記第2のセットの導体を前記トレンチ内に延ばし、それによって隣接するピラーのフローティングゲートを前記第2の方向で互いに絶縁し、選択トランジスタゲートとして役立つようにするステップを含む請求項31記載の方法。
- 前記1つのセットの導体を形成するステップは、隣接するピラーのフローティングゲート間のチャネル内に前記第1の方向に前記1つのセットの導体を延ばし、それによって隣接するピラーのフローティングゲートを前記第1の方向で互いに絶縁するステップを含む請求項32記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/732,967 US7049652B2 (en) | 2003-12-10 | 2003-12-10 | Pillar cell flash memory technology |
US10/732,967 | 2003-12-10 | ||
PCT/US2004/040324 WO2005062378A1 (en) | 2003-12-10 | 2004-12-01 | Pillar cell flash memory technology |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007520876A true JP2007520876A (ja) | 2007-07-26 |
JP5009626B2 JP5009626B2 (ja) | 2012-08-22 |
Family
ID=34652977
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006543889A Expired - Fee Related JP5009626B2 (ja) | 2003-12-10 | 2004-12-01 | ピラー構造セルのフラッシュメモリ技術 |
Country Status (7)
Country | Link |
---|---|
US (3) | US7049652B2 (ja) |
EP (1) | EP1692721A1 (ja) |
JP (1) | JP5009626B2 (ja) |
KR (1) | KR20070007256A (ja) |
CN (1) | CN1906756B (ja) |
TW (1) | TWI267199B (ja) |
WO (1) | WO2005062378A1 (ja) |
Families Citing this family (132)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6888755B2 (en) * | 2002-10-28 | 2005-05-03 | Sandisk Corporation | Flash memory cell arrays having dual control gates per memory cell charge storage element |
US7323367B1 (en) * | 2002-12-31 | 2008-01-29 | Transmeta Corporation | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions |
US6936898B2 (en) | 2002-12-31 | 2005-08-30 | Transmeta Corporation | Diagonal deep well region for routing body-bias voltage for MOSFETS in surface well regions |
US7174528B1 (en) | 2003-10-10 | 2007-02-06 | Transmeta Corporation | Method and apparatus for optimizing body bias connections in CMOS circuits using a deep n-well grid structure |
JP3966850B2 (ja) * | 2003-11-20 | 2007-08-29 | 株式会社東芝 | 半導体装置およびその製造方法 |
US7148538B2 (en) * | 2003-12-17 | 2006-12-12 | Micron Technology, Inc. | Vertical NAND flash memory array |
US7645673B1 (en) * | 2004-02-03 | 2010-01-12 | Michael Pelham | Method for generating a deep N-well pattern for an integrated circuit design |
US7238575B2 (en) * | 2004-03-10 | 2007-07-03 | Promos Technologies, Inc. | Fabrication of conductive lines interconnecting conductive gates in nonvolatile memories, and non-volatile memory structures |
US7148104B2 (en) * | 2004-03-10 | 2006-12-12 | Promos Technologies Inc. | Fabrication of conductive lines interconnecting first conductive gates in nonvolatile memories having second conductive gates provided by conductive gate lines, wherein the adjacent conductive gate lines for the adjacent columns are spaced from each other, and non-volatile memory structures |
US7388260B1 (en) | 2004-03-31 | 2008-06-17 | Transmeta Corporation | Structure for spanning gap in body-bias voltage routing structure |
US7151027B1 (en) * | 2004-06-01 | 2006-12-19 | Spansion Llc | Method and device for reducing interface area of a memory device |
JP2006012871A (ja) * | 2004-06-22 | 2006-01-12 | Nec Electronics Corp | 不揮発性半導体記憶装置及びその製造方法 |
US7190616B2 (en) * | 2004-07-19 | 2007-03-13 | Micron Technology, Inc. | In-service reconfigurable DRAM and flash memory device |
US7449744B1 (en) * | 2004-08-03 | 2008-11-11 | Nanostar Corporation | Non-volatile electrically alterable memory cell and use thereof in multi-function memory array |
TWI246188B (en) * | 2004-08-12 | 2005-12-21 | Promos Technologies Inc | Flash memory structure and fabrication method thereof |
US7189627B2 (en) * | 2004-08-19 | 2007-03-13 | Texas Instruments Incorporated | Method to improve SRAM performance and stability |
WO2006030380A1 (en) * | 2004-09-15 | 2006-03-23 | Koninklijke Philips Electronics N.V. | A sonos memory device with optimized shallow trench isolation |
JP4970760B2 (ja) * | 2004-09-15 | 2012-07-11 | 三星電子株式会社 | 半導体メモリ装置のライン配置構造 |
JP3962769B2 (ja) | 2004-11-01 | 2007-08-22 | 株式会社Genusion | 不揮発性半導体記憶装置およびその書込方法 |
TWI270199B (en) * | 2005-01-31 | 2007-01-01 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method and operating method thereof |
EP1727152B1 (fr) * | 2005-05-18 | 2008-12-24 | STMicroelectronics SA | Architecture de mémoire EEPROM |
US7305647B1 (en) | 2005-07-28 | 2007-12-04 | Transmeta Corporation | Using standard pattern tiles and custom pattern tiles to generate a semiconductor design layout having a deep well structure for routing body-bias voltage |
KR100849852B1 (ko) * | 2005-08-09 | 2008-08-01 | 삼성전자주식회사 | 비휘발성 반도체 집적 회로 장치 및 이의 제조 방법 |
US7372732B2 (en) * | 2005-11-23 | 2008-05-13 | Macronix International Co., Ltd. | Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell |
TWI281753B (en) * | 2005-12-13 | 2007-05-21 | Powerchip Semiconductor Corp | Non-volatile memory and manufacturing method and operating method thereof |
JP2007201244A (ja) * | 2006-01-27 | 2007-08-09 | Renesas Technology Corp | 半導体装置 |
US7388781B2 (en) * | 2006-03-06 | 2008-06-17 | Sandisk Il Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
US8848442B2 (en) * | 2006-03-06 | 2014-09-30 | Sandisk Il Ltd. | Multi-bit-per-cell flash memory device with non-bijective mapping |
US7951669B2 (en) | 2006-04-13 | 2011-05-31 | Sandisk Corporation | Methods of making flash memory cell arrays having dual control gates per memory cell charge storage element |
US8852851B2 (en) | 2006-07-10 | 2014-10-07 | Micron Technology, Inc. | Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same |
KR101427362B1 (ko) * | 2006-09-19 | 2014-08-07 | 샌디스크 테크놀로지스, 인코포레이티드 | 기판 트렌치에 스페이서로 형성된 플로팅 게이트를 구비하는 비휘발성 메모리 셀의 어레이 |
US7696044B2 (en) * | 2006-09-19 | 2010-04-13 | Sandisk Corporation | Method of making an array of non-volatile memory cells with floating gates formed of spacers in substrate trenches |
US7646054B2 (en) * | 2006-09-19 | 2010-01-12 | Sandisk Corporation | Array of non-volatile memory cells with floating gates formed of spacers in substrate trenches |
US7423912B2 (en) | 2006-09-19 | 2008-09-09 | Atmel Corporation | SONOS memory array with improved read disturb characteristic |
US7961511B2 (en) * | 2006-09-26 | 2011-06-14 | Sandisk Corporation | Hybrid programming methods and systems for non-volatile memory storage elements |
US7800161B2 (en) * | 2006-12-21 | 2010-09-21 | Sandisk Corporation | Flash NAND memory cell array with charge storage elements positioned in trenches |
US7642160B2 (en) * | 2006-12-21 | 2010-01-05 | Sandisk Corporation | Method of forming a flash NAND memory cell array with charge storage elements positioned in trenches |
JP4772656B2 (ja) * | 2006-12-21 | 2011-09-14 | 株式会社東芝 | 不揮発性半導体メモリ |
JP2008166442A (ja) | 2006-12-27 | 2008-07-17 | Spansion Llc | 半導体装置およびその製造方法 |
US7898009B2 (en) * | 2007-02-22 | 2011-03-01 | American Semiconductor, Inc. | Independently-double-gated transistor memory (IDGM) |
US7851851B2 (en) * | 2007-03-27 | 2010-12-14 | Sandisk 3D Llc | Three dimensional NAND memory |
US7745265B2 (en) * | 2007-03-27 | 2010-06-29 | Sandisk 3D, Llc | Method of making three dimensional NAND memory |
US7808038B2 (en) * | 2007-03-27 | 2010-10-05 | Sandisk 3D Llc | Method of making three dimensional NAND memory |
US7848145B2 (en) * | 2007-03-27 | 2010-12-07 | Sandisk 3D Llc | Three dimensional NAND memory |
US7575973B2 (en) | 2007-03-27 | 2009-08-18 | Sandisk 3D Llc | Method of making three dimensional NAND memory |
US7514321B2 (en) * | 2007-03-27 | 2009-04-07 | Sandisk 3D Llc | Method of making three dimensional NAND memory |
US8030161B2 (en) * | 2007-05-23 | 2011-10-04 | Nanosys, Inc. | Gate electrode for a nonvolatile memory cell |
US8012830B2 (en) | 2007-08-08 | 2011-09-06 | Spansion Llc | ORO and ORPRO with bit line trench to suppress transport program disturb |
US7776688B2 (en) * | 2007-08-08 | 2010-08-17 | Spansion Llc | Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics |
JP5466816B2 (ja) * | 2007-08-09 | 2014-04-09 | ピーエスフォー ルクスコ エスエイアールエル | 縦型mosトランジスタの製造方法 |
JP2009049230A (ja) * | 2007-08-21 | 2009-03-05 | Panasonic Corp | 半導体記憶装置及びその製造方法 |
US8320191B2 (en) | 2007-08-30 | 2012-11-27 | Infineon Technologies Ag | Memory cell arrangement, method for controlling a memory cell, memory array and electronic device |
US7613042B2 (en) * | 2007-11-05 | 2009-11-03 | Spansion Llc | Decoding system capable of reducing sector select area overhead for flash memory |
JP5367256B2 (ja) * | 2007-12-17 | 2013-12-11 | スパンション エルエルシー | 半導体装置およびその製造方法 |
US8546152B2 (en) * | 2007-12-19 | 2013-10-01 | Sandisk Technologies Inc. | Enhanced endpoint detection in non-volatile memory fabrication processes |
US7615447B2 (en) * | 2007-12-19 | 2009-11-10 | Sandisk Corporation | Composite charge storage structure formation in non-volatile memory using etch stop technologies |
US7957192B2 (en) * | 2007-12-31 | 2011-06-07 | Cypress Semiconductor Corporation | Read and volatile NV standby disturb |
US8394683B2 (en) * | 2008-01-15 | 2013-03-12 | Micron Technology, Inc. | Methods of forming semiconductor constructions, and methods of forming NAND unit cells |
JP2009206492A (ja) * | 2008-01-31 | 2009-09-10 | Toshiba Corp | 半導体装置 |
US20090242961A1 (en) * | 2008-03-31 | 2009-10-01 | Sanh Tang | Recessed channel select gate for a memory device |
US7989307B2 (en) | 2008-05-05 | 2011-08-02 | Micron Technology, Inc. | Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same |
US10151981B2 (en) * | 2008-05-22 | 2018-12-11 | Micron Technology, Inc. | Methods of forming structures supported by semiconductor substrates |
US8344429B2 (en) | 2008-09-17 | 2013-01-01 | Infineon Technologies Ag | Compact memory arrays |
US7851846B2 (en) * | 2008-12-03 | 2010-12-14 | Silicon Storage Technology, Inc. | Non-volatile memory cell with buried select gate, and method of making same |
US8796155B2 (en) | 2008-12-04 | 2014-08-05 | Micron Technology, Inc. | Methods of fabricating substrates |
US8273634B2 (en) * | 2008-12-04 | 2012-09-25 | Micron Technology, Inc. | Methods of fabricating substrates |
US8247302B2 (en) * | 2008-12-04 | 2012-08-21 | Micron Technology, Inc. | Methods of fabricating substrates |
US8174067B2 (en) | 2008-12-08 | 2012-05-08 | Fairchild Semiconductor Corporation | Trench-based power semiconductor devices with increased breakdown voltage characteristics |
US20100161888A1 (en) * | 2008-12-22 | 2010-06-24 | Unity Semiconductor Corporation | Data storage system with non-volatile memory using both page write and block program and block erase |
JP2010199235A (ja) * | 2009-02-24 | 2010-09-09 | Toshiba Corp | 不揮発性半導体記憶装置 |
US8268543B2 (en) | 2009-03-23 | 2012-09-18 | Micron Technology, Inc. | Methods of forming patterns on substrates |
US7776677B1 (en) * | 2009-03-30 | 2010-08-17 | Semiconductor Components Industries, Llc | Method of forming an EEPROM device and structure therefor |
US9330934B2 (en) * | 2009-05-18 | 2016-05-03 | Micron Technology, Inc. | Methods of forming patterns on substrates |
JP2011023637A (ja) * | 2009-07-17 | 2011-02-03 | Toshiba Corp | 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法 |
SG10201700467UA (en) | 2010-02-07 | 2017-02-27 | Zeno Semiconductor Inc | Semiconductor memory device having electrically floating body transistor, and having both volatile and non-volatile functionality and method |
TWI442550B (zh) * | 2010-02-12 | 2014-06-21 | Macronix Int Co Ltd | 位元線結構、半導體元件及其形成方法 |
CN102194822B (zh) * | 2010-03-01 | 2014-12-17 | 旺宏电子股份有限公司 | 位元线结构、半导体元件及其形成方法 |
JP5642983B2 (ja) * | 2010-03-11 | 2014-12-17 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
US8455341B2 (en) | 2010-09-02 | 2013-06-04 | Micron Technology, Inc. | Methods of forming features of integrated circuitry |
WO2012033533A1 (en) * | 2010-09-09 | 2012-03-15 | Aplus Flash Technology, Inc. | Compact flotox-based combo nvm design without sacrificing endurance cycles for 1-die data and code storage |
KR101152446B1 (ko) | 2010-12-08 | 2012-06-01 | 한양대학교 산학협력단 | 프린징 효과 및 정전차폐를 이용하는 플래시 메모리 |
US8502302B2 (en) * | 2011-05-02 | 2013-08-06 | Alpha And Omega Semiconductor Incorporated | Integrating Schottky diode into power MOSFET |
KR101780274B1 (ko) * | 2011-05-04 | 2017-09-21 | 에스케이하이닉스 주식회사 | 비휘발성 메모리 장치 |
US8575032B2 (en) | 2011-05-05 | 2013-11-05 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
JP2013069947A (ja) * | 2011-09-26 | 2013-04-18 | Toshiba Corp | 不揮発性半導体記憶装置の製造方法および不揮発性半導体記憶装置 |
CN103021855B (zh) * | 2011-09-27 | 2015-04-01 | 中芯国际集成电路制造(上海)有限公司 | 分离栅闪存的有源区制造方法 |
US9117752B2 (en) * | 2011-11-03 | 2015-08-25 | Macronix International Co., Ltd. | Kink poly structure for improving random single bit failure |
US9177794B2 (en) | 2012-01-13 | 2015-11-03 | Micron Technology, Inc. | Methods of patterning substrates |
US8629048B1 (en) | 2012-07-06 | 2014-01-14 | Micron Technology, Inc. | Methods of forming a pattern on a substrate |
JP2014063771A (ja) * | 2012-09-19 | 2014-04-10 | Toshiba Corp | 半導体装置 |
US9224474B2 (en) * | 2013-01-09 | 2015-12-29 | Macronix International Co., Ltd. | P-channel 3D memory array and methods to program and erase the same at bit level and block level utilizing band-to-band and fowler-nordheim tunneling principals |
US9378821B1 (en) | 2013-01-18 | 2016-06-28 | Cypress Semiconductor Corporation | Endurance of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells |
US9368408B2 (en) * | 2013-12-27 | 2016-06-14 | Infineon Technologies Dresden Gmbh | Method of manufacturing a semiconductor device with buried channel/body zone and semiconductor device |
US9287280B2 (en) * | 2014-07-09 | 2016-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method to improve memory cell erasure |
US9767045B2 (en) | 2014-08-29 | 2017-09-19 | Memory Technologies Llc | Control for authenticated accesses to a memory device |
FR3030883B1 (fr) * | 2014-12-17 | 2017-12-22 | Stmicroelectronics Rousset | Cellule memoire a grille de selection verticale formee dans un substrat de type fdsoi |
CN106328653B (zh) * | 2015-07-07 | 2023-04-18 | 物联记忆体科技股份有限公司 | 非易失性存储器及其制造方法 |
KR102432793B1 (ko) * | 2015-09-30 | 2022-08-17 | 에스케이하이닉스 주식회사 | 반도체 장치 |
KR102396734B1 (ko) * | 2015-11-23 | 2022-05-12 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그것의 동작 방법 |
US10074438B2 (en) | 2016-06-10 | 2018-09-11 | Cypress Semiconductor Corporation | Methods and devices for reducing program disturb in non-volatile memory cell arrays |
US9685239B1 (en) * | 2016-10-12 | 2017-06-20 | Pegasus Semiconductor (Beijing) Co., Ltd | Field sub-bitline nor flash array |
US10381085B2 (en) | 2016-10-27 | 2019-08-13 | Micron Technogy, Inc. | Erasing memory cells |
US10163917B2 (en) * | 2016-11-01 | 2018-12-25 | Micron Technology, Inc. | Cell disturb prevention using a leaker device to reduce excess charge from an electronic device |
US9997253B1 (en) | 2016-12-08 | 2018-06-12 | Cypress Semiconductor Corporation | Non-volatile memory array with memory gate line and source line scrambling |
US10424374B2 (en) * | 2017-04-28 | 2019-09-24 | Micron Technology, Inc. | Programming enhancement in self-selecting memory |
KR101999902B1 (ko) * | 2017-11-15 | 2019-10-01 | 도실리콘 씨오., 엘티디. | 페이싱바를 가지는 낸드 플래쉬 메모리 장치 및 그의 제조 방법 |
US10424730B2 (en) | 2018-02-09 | 2019-09-24 | Micron Technology, Inc. | Tapered memory cell profiles |
US10693065B2 (en) | 2018-02-09 | 2020-06-23 | Micron Technology, Inc. | Tapered cell profile and fabrication |
US10854813B2 (en) | 2018-02-09 | 2020-12-01 | Micron Technology, Inc. | Dopant-modulated etching for memory devices |
US10541364B2 (en) | 2018-02-09 | 2020-01-21 | Micron Technology, Inc. | Memory cells with asymmetrical electrode interfaces |
FR3080949B1 (fr) * | 2018-05-04 | 2021-05-28 | St Microelectronics Rousset | Dispositif de memoire non volatile du type a piegeage de charges et procede de fabrication |
US10614867B2 (en) * | 2018-07-31 | 2020-04-07 | Spin Memory, Inc. | Patterning of high density small feature size pillar structures |
US11127827B2 (en) | 2018-09-26 | 2021-09-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Control gate strap layout to improve a word line etch process window |
US10847526B1 (en) | 2019-07-26 | 2020-11-24 | Micron Technology, Inc. | Microelectronic devices including staircase structures, and related memory devices and electronic systems |
TWI702604B (zh) * | 2019-08-23 | 2020-08-21 | 卡比科技有限公司 | 非揮發性記憶體裝置及非揮發式記憶體陣列 |
CN114303241A (zh) * | 2019-08-28 | 2022-04-08 | 美光科技公司 | 具有双晶体管垂直存储器单元及共享沟道区域的存储器装置 |
WO2021056513A1 (en) | 2019-09-29 | 2021-04-01 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional memory devices and methods for forming the same |
CN112635488A (zh) | 2019-09-29 | 2021-04-09 | 长江存储科技有限责任公司 | 三维存储器件及其形成方法 |
CN110785846B (zh) | 2019-09-29 | 2021-03-23 | 长江存储科技有限责任公司 | 三维存储器件及其形成方法 |
US11017851B1 (en) * | 2019-11-26 | 2021-05-25 | Cypress Semiconductor Corporation | Silicon-oxide-nitride-oxide-silicon based multi level non-volatile memory device and methods of operation thereof |
US11588031B2 (en) * | 2019-12-30 | 2023-02-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure for memory device and method for forming the same |
EP4073584A1 (en) | 2020-02-14 | 2022-10-19 | Synopsys, Inc. | Skeleton representation of layouts for the development of lithographic masks |
US11393535B2 (en) * | 2020-02-26 | 2022-07-19 | Silicon Storage Technology, Inc. | Ultra-precise tuning of analog neural memory cells in a deep learning artificial neural network |
JP2021141185A (ja) * | 2020-03-05 | 2021-09-16 | キオクシア株式会社 | 半導体記憶装置 |
TWI727690B (zh) * | 2020-03-05 | 2021-05-11 | 華邦電子股份有限公司 | 非揮發性記憶體裝置及其製造方法 |
JP2021150573A (ja) * | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | 半導体記憶装置 |
US20210408117A1 (en) * | 2020-06-29 | 2021-12-30 | Taiwan Semiconductor Manufacturing Company Limited | Multi-gate selector switches for memory cells and methods of forming the same |
CN114068562A (zh) | 2020-07-29 | 2022-02-18 | 联华电子股份有限公司 | 半导体存储装置以及其制作方法 |
CN111799165B (zh) * | 2020-09-09 | 2020-12-04 | 南京晶驱集成电路有限公司 | 一种半导体结构的制备方法 |
JP2022052505A (ja) * | 2020-09-23 | 2022-04-04 | キオクシア株式会社 | メモリデバイス |
CN114695365A (zh) * | 2020-12-30 | 2022-07-01 | 无锡华润上华科技有限公司 | Eeprom器件及其制备方法 |
US11631772B2 (en) * | 2021-01-13 | 2023-04-18 | Globalfoundries U.S. Inc. | Non-volatile memory structure using semiconductor layer as floating gate and bulk semiconductor substrate as channel region |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02275668A (ja) * | 1988-11-10 | 1990-11-09 | Texas Instr Inc <Ti> | フローティングゲートメモリアレイ |
JPH04335578A (ja) * | 1991-05-10 | 1992-11-24 | Sony Corp | 不揮発性半導体装置の製造方法 |
JPH05211338A (ja) * | 1991-10-09 | 1993-08-20 | Mitsubishi Electric Corp | 不揮発性半導体装置 |
JPH05275713A (ja) * | 1991-12-19 | 1993-10-22 | Philips Gloeilampenfab:Nv | 不揮発性メモリ装置及びその製造方法 |
JP2000188384A (ja) * | 1998-12-22 | 2000-07-04 | Toshiba Corp | 不揮発性半導体記憶装置 |
US6151248A (en) * | 1999-06-30 | 2000-11-21 | Sandisk Corporation | Dual floating gate EEPROM cell array with steering gates shared by adjacent cells |
US6268248B1 (en) * | 1997-12-23 | 2001-07-31 | Texas Instruments Incorporated | Method of fabricating a source line in flash memory having STI structures |
US6429081B1 (en) * | 2001-05-17 | 2002-08-06 | Taiwan Semiconductor Manufacturing Company | Parasitic surface transfer transistor cell (PASTT cell) for bi-level and multi-level NAND flash memory |
JP2005506685A (ja) * | 2001-05-18 | 2005-03-03 | サンディスク コーポレイション | 基板トレンチを利用する不揮発性メモリセル |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5095344A (en) * | 1988-06-08 | 1992-03-10 | Eliyahou Harari | Highly compact eprom and flash eeprom devices |
US5051796A (en) * | 1988-11-10 | 1991-09-24 | Texas Instruments Incorporated | Cross-point contact-free array with a high-density floating-gate structure |
US5120571A (en) * | 1988-11-10 | 1992-06-09 | Texas Instruments Incorporated | Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates |
IT1235690B (it) * | 1989-04-07 | 1992-09-21 | Sgs Thomson Microelectronics | Procedimento di fabbricazione per una matrice di celle eprom organizzate a tovaglia. |
DE69033262T2 (de) * | 1989-04-13 | 2000-02-24 | Sandisk Corp | EEPROM-Karte mit Austauch von fehlerhaften Speicherzellen und Zwischenspeicher |
US5071782A (en) * | 1990-06-28 | 1991-12-10 | Texas Instruments Incorporated | Vertical memory cell array and method of fabrication |
JP3036008B2 (ja) * | 1990-07-18 | 2000-04-24 | 日本電気株式会社 | 半導体記憶装置 |
US5343063A (en) * | 1990-12-18 | 1994-08-30 | Sundisk Corporation | Dense vertical programmable read only memory cell structure and processes for making them |
US5270979A (en) * | 1991-03-15 | 1993-12-14 | Sundisk Corporation | Method for optimum erasing of EEPROM |
US6230233B1 (en) * | 1991-09-13 | 2001-05-08 | Sandisk Corporation | Wear leveling techniques for flash EEPROM systems |
US5712180A (en) * | 1992-01-14 | 1998-01-27 | Sundisk Corporation | EEPROM with split gate source side injection |
US6222762B1 (en) * | 1992-01-14 | 2001-04-24 | Sandisk Corporation | Multi-state memory |
US5467305A (en) * | 1992-03-12 | 1995-11-14 | International Business Machines Corporation | Three-dimensional direct-write EEPROM arrays and fabrication methods |
US5297082A (en) * | 1992-11-12 | 1994-03-22 | Micron Semiconductor, Inc. | Shallow trench source eprom cell |
KR100205309B1 (ko) * | 1996-07-23 | 1999-07-01 | 구본준 | 비휘발성 메모리셀 및 이 비휘발성 메모리셀을 프로그래밍하는 방법 |
US6161034A (en) * | 1999-02-02 | 2000-12-12 | Senorx, Inc. | Methods and chemical preparations for time-limited marking of biopsy sites |
US6118147A (en) * | 1998-07-07 | 2000-09-12 | Advanced Micro Devices, Inc. | Double density non-volatile memory cells |
US6248633B1 (en) * | 1999-10-25 | 2001-06-19 | Halo Lsi Design & Device Technology, Inc. | Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory |
EP1104023A1 (en) * | 1999-11-26 | 2001-05-30 | STMicroelectronics S.r.l. | Process for manufacturing electronic devices comprising non-volatile memory cells |
JP2001154903A (ja) * | 1999-11-26 | 2001-06-08 | Nec Corp | 無線ネットワーク通信システム |
US6512263B1 (en) * | 2000-09-22 | 2003-01-28 | Sandisk Corporation | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming |
US6576537B2 (en) * | 2001-08-08 | 2003-06-10 | Vanguard International Semiconductor Corp. | Flash memory cell and method for fabricating a flash memory cell |
US6525369B1 (en) * | 2002-05-13 | 2003-02-25 | Ching-Yuan Wu | Self-aligned split-gate flash memory cell and its contactless flash memory arrays |
US20040006621A1 (en) * | 2002-06-27 | 2004-01-08 | Bellinson Craig Adam | Content filtering for web browsing |
-
2003
- 2003-12-10 US US10/732,967 patent/US7049652B2/en not_active Expired - Lifetime
-
2004
- 2004-12-01 WO PCT/US2004/040324 patent/WO2005062378A1/en active Application Filing
- 2004-12-01 KR KR1020067011518A patent/KR20070007256A/ko not_active Application Discontinuation
- 2004-12-01 EP EP04812767A patent/EP1692721A1/en not_active Withdrawn
- 2004-12-01 CN CN2004800407366A patent/CN1906756B/zh not_active Expired - Fee Related
- 2004-12-01 JP JP2006543889A patent/JP5009626B2/ja not_active Expired - Fee Related
- 2004-12-10 TW TW093138465A patent/TWI267199B/zh not_active IP Right Cessation
-
2006
- 2006-03-29 US US11/277,907 patent/US7253055B2/en not_active Expired - Lifetime
-
2007
- 2007-07-10 US US11/775,808 patent/US20070252192A1/en not_active Abandoned
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02275668A (ja) * | 1988-11-10 | 1990-11-09 | Texas Instr Inc <Ti> | フローティングゲートメモリアレイ |
JPH04335578A (ja) * | 1991-05-10 | 1992-11-24 | Sony Corp | 不揮発性半導体装置の製造方法 |
JPH05211338A (ja) * | 1991-10-09 | 1993-08-20 | Mitsubishi Electric Corp | 不揮発性半導体装置 |
JPH05275713A (ja) * | 1991-12-19 | 1993-10-22 | Philips Gloeilampenfab:Nv | 不揮発性メモリ装置及びその製造方法 |
US6268248B1 (en) * | 1997-12-23 | 2001-07-31 | Texas Instruments Incorporated | Method of fabricating a source line in flash memory having STI structures |
JP2000188384A (ja) * | 1998-12-22 | 2000-07-04 | Toshiba Corp | 不揮発性半導体記憶装置 |
US6151248A (en) * | 1999-06-30 | 2000-11-21 | Sandisk Corporation | Dual floating gate EEPROM cell array with steering gates shared by adjacent cells |
US6429081B1 (en) * | 2001-05-17 | 2002-08-06 | Taiwan Semiconductor Manufacturing Company | Parasitic surface transfer transistor cell (PASTT cell) for bi-level and multi-level NAND flash memory |
JP2005506685A (ja) * | 2001-05-18 | 2005-03-03 | サンディスク コーポレイション | 基板トレンチを利用する不揮発性メモリセル |
Also Published As
Publication number | Publication date |
---|---|
JP5009626B2 (ja) | 2012-08-22 |
US20070252192A1 (en) | 2007-11-01 |
US7049652B2 (en) | 2006-05-23 |
WO2005062378A1 (en) | 2005-07-07 |
US20060160305A1 (en) | 2006-07-20 |
CN1906756A (zh) | 2007-01-31 |
KR20070007256A (ko) | 2007-01-15 |
US20050127428A1 (en) | 2005-06-16 |
TW200541081A (en) | 2005-12-16 |
EP1692721A1 (en) | 2006-08-23 |
TWI267199B (en) | 2006-11-21 |
CN1906756B (zh) | 2012-01-11 |
US7253055B2 (en) | 2007-08-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5009626B2 (ja) | ピラー構造セルのフラッシュメモリ技術 | |
US8824209B2 (en) | Non-volatile memory device having vertical structure and method of operating the same | |
US7820516B2 (en) | Methods of manufacturing non-volatile memory devices having a vertical channel | |
US9564221B2 (en) | Non-volatile memory device having vertical structure and method of operating the same | |
US9036421B2 (en) | Strings of memory cells having string select gates, memory devices incorporating such strings, and methods of accessing and forming the same | |
US7829404B2 (en) | Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates | |
US7638835B2 (en) | Double density NROM with nitride strips (DDNS) | |
KR20230042417A (ko) | 3차원 어레이에서 용량 결합된 비휘발성 박막 트랜지스터 스트링 | |
US9224746B2 (en) | Inverted-T word line and formation for non-volatile storage | |
JP4065671B2 (ja) | 不揮発性半導体記憶装置、その製造方法及びその動作方法 | |
JP2007201244A (ja) | 半導体装置 | |
JP2008010868A (ja) | 垂直チャンネルを有する不揮発性メモリ装置およびその製造方法 | |
JP2007527614A (ja) | 耐久性が改善された分離トランジスタメモリ及びその製造方法 | |
US6392927B2 (en) | Cell array, operating method of the same and manufacturing method of the same | |
박세환 | 3-Dimensional NAND flash memory having Tied Bit-line and Ground Select Transistor (TiGer) |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20071126 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20110615 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20110712 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20111007 |
|
A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20111017 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120112 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20120508 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20120531 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5009626 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150608 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150608 Year of fee payment: 3 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20150608 Year of fee payment: 3 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |