JP4662943B2 - コンタクトの形成中、コンタクトホール幅の増大を防ぐ方法 - Google Patents

コンタクトの形成中、コンタクトホール幅の増大を防ぐ方法 Download PDF

Info

Publication number
JP4662943B2
JP4662943B2 JP2006539499A JP2006539499A JP4662943B2 JP 4662943 B2 JP4662943 B2 JP 4662943B2 JP 2006539499 A JP2006539499 A JP 2006539499A JP 2006539499 A JP2006539499 A JP 2006539499A JP 4662943 B2 JP4662943 B2 JP 4662943B2
Authority
JP
Japan
Prior art keywords
contact hole
layer
contact
barrier layer
native oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006539499A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007511087A (ja
JP2007511087A5 (enExample
Inventor
エム． ホッパー ドーン
博幸 木下
ウー クリスティ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2007511087A publication Critical patent/JP2007511087A/ja
Publication of JP2007511087A5 publication Critical patent/JP2007511087A5/ja
Application granted granted Critical
Publication of JP4662943B2 publication Critical patent/JP4662943B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2006539499A 2003-11-08 2004-10-08 コンタクトの形成中、コンタクトホール幅の増大を防ぐ方法 Expired - Fee Related JP4662943B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/705,631 US7005387B2 (en) 2003-11-08 2003-11-08 Method for preventing an increase in contact hole width during contact formation
PCT/US2004/033417 WO2005048342A1 (en) 2003-11-08 2004-10-08 Method for preventing an increase in contact hole width during contact formation

Publications (3)

Publication Number Publication Date
JP2007511087A JP2007511087A (ja) 2007-04-26
JP2007511087A5 JP2007511087A5 (enExample) 2007-11-29
JP4662943B2 true JP4662943B2 (ja) 2011-03-30

Family

ID=34552414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006539499A Expired - Fee Related JP4662943B2 (ja) 2003-11-08 2004-10-08 コンタクトの形成中、コンタクトホール幅の増大を防ぐ方法

Country Status (8)

Country Link
US (1) US7005387B2 (enExample)
JP (1) JP4662943B2 (enExample)
KR (1) KR101180977B1 (enExample)
CN (1) CN1883045A (enExample)
DE (1) DE112004002156T5 (enExample)
GB (1) GB2423635B (enExample)
TW (1) TWI359475B (enExample)
WO (1) WO2005048342A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080038910A1 (en) * 2006-08-10 2008-02-14 Advanced Micro Devices, Inc. Multiple lithography for reduced negative feature corner rounding
US20090050471A1 (en) * 2007-08-24 2009-02-26 Spansion Llc Process of forming an electronic device including depositing layers within openings
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
JP6494940B2 (ja) * 2013-07-25 2019-04-03 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ 異なるサイズのフィーチャへのボイドフリータングステン充填
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
KR102607331B1 (ko) * 2018-07-13 2023-11-29 에스케이하이닉스 주식회사 고종횡비 구조를 위한 갭필 방법 및 그를 이용한 반도체장치 제조 방법
DE112023002169T5 (de) 2023-01-05 2025-02-27 Fuji Electric Co., Ltd. Halbleitervorrichtung und Herstellungsverfahren dafür

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513411A (ja) * 1991-07-02 1993-01-22 Nec Corp 半導体装置の製造方法
JPH0661181A (ja) 1992-08-11 1994-03-04 Sony Corp バリアメタルの形成方法
JP3237917B2 (ja) * 1992-09-22 2001-12-10 沖電気工業株式会社 半導体素子の製造方法
JPH06349824A (ja) * 1993-06-10 1994-12-22 Toshiba Corp 半導体装置の製造方法
JPH09116009A (ja) * 1995-10-23 1997-05-02 Sony Corp 接続孔の形成方法
JPH09139358A (ja) * 1995-11-13 1997-05-27 Sony Corp 半導体装置の製造方法
US5985762A (en) * 1997-05-19 1999-11-16 International Business Machines Corporation Method of forming a self-aligned copper diffusion barrier in vias
TW388095B (en) * 1997-05-20 2000-04-21 United Microelectronics Corp Method for improving planarization of dielectric layer in interconnect metal process
JP3201318B2 (ja) * 1997-11-05 2001-08-20 日本電気株式会社 半導体装置の製造方法
US5994211A (en) * 1997-11-21 1999-11-30 Lsi Logic Corporation Method and composition for reducing gate oxide damage during RF sputter clean
US6303505B1 (en) * 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6511575B1 (en) * 1998-11-12 2003-01-28 Canon Kabushiki Kaisha Treatment apparatus and method utilizing negative hydrogen ion
KR100277086B1 (ko) * 1999-01-02 2000-12-15 윤종용 반도체 장치 및 그 제조 방법
JP4221859B2 (ja) * 1999-02-12 2009-02-12 株式会社デンソー 半導体装置の製造方法
US6348709B1 (en) * 1999-03-15 2002-02-19 Micron Technology, Inc. Electrical contact for high dielectric constant capacitors and method for fabricating the same
JP2000323571A (ja) * 1999-05-14 2000-11-24 Sony Corp 半導体装置の製造方法
KR100316721B1 (ko) * 2000-01-29 2001-12-12 윤종용 실리사이드막을 구비한 반도체소자의 제조방법
KR20010077743A (ko) * 2000-02-08 2001-08-20 박종섭 비트 라인 및 그 제조 방법
US6498091B1 (en) * 2000-11-01 2002-12-24 Applied Materials, Inc. Method of using a barrier sputter reactor to remove an underlying barrier layer
US6624066B2 (en) 2001-02-14 2003-09-23 Texas Instruments Incorporated Reliable interconnects with low via/contact resistance
US20030073304A1 (en) * 2001-10-16 2003-04-17 Applied Materials, Inc. Selective tungsten stud as copper diffusion barrier to silicon contact

Also Published As

Publication number Publication date
TW200524077A (en) 2005-07-16
CN1883045A (zh) 2006-12-20
US20050101148A1 (en) 2005-05-12
KR20060107763A (ko) 2006-10-16
KR101180977B1 (ko) 2012-09-07
US7005387B2 (en) 2006-02-28
WO2005048342A1 (en) 2005-05-26
JP2007511087A (ja) 2007-04-26
GB2423635A (en) 2006-08-30
GB0608285D0 (en) 2006-06-07
GB2423635B (en) 2007-05-30
DE112004002156T5 (de) 2006-09-14
TWI359475B (en) 2012-03-01

Similar Documents

Publication Publication Date Title
US9837304B2 (en) Sidewall protection scheme for contact formation
JP4587774B2 (ja) 半導体デバイスを形成する方法
JP4282616B2 (ja) 半導体装置の製造方法
KR20090005747A (ko) 반도체 소자의 제조방법
JP2005340808A (ja) 半導体装置のバリア構造
JP4662943B2 (ja) コンタクトの形成中、コンタクトホール幅の増大を防ぐ方法
TWI387008B (zh) 含矽化物纖維移除程序之半導體製程
US7067417B2 (en) Methods of removing resistive remnants from contact holes using silicidation
JP2005142481A (ja) 半導体装置の製造方法
JP2008305921A (ja) 半導体装置及びその製造方法
KR100503312B1 (ko) 반도체 소자의 콘택 전극 제조 방법
JP4457884B2 (ja) 半導体装置
US6734098B2 (en) Method for fabricating cobalt salicide contact
US7341955B2 (en) Method for fabricating semiconductor device
JP2005197710A (ja) 半導体装置製造方法
JP2006191056A (ja) リセスされたストレージノードコンタクトプラグを有する半導体メモリ装置の製造方法
KR100729905B1 (ko) 반도체 소자의 캐패시터 제조 방법
JP2006191053A (ja) 半導体メモリ装置の製造方法
JP2006203109A (ja) 半導体装置およびその製造方法
KR100741269B1 (ko) 반도체 소자의 금속배선 형성 방법
KR100755053B1 (ko) 반도체 소자의 비트라인 형성 방법
KR100691483B1 (ko) 반도체 소자의 제조 방법
TW452865B (en) Method for forming conductive area by ionized metal plasma
KR100552840B1 (ko) 반도체 소자의 선택적 실리사이드 형성 방법 및 이실리사이드막을 갖는 반도체 소자
JP2004055664A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071009

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20071009

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20100421

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20100806

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20100818

RD05 Notification of revocation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7425

Effective date: 20100902

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20101117

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20101208

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20110104

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140114

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees