TW452865B - Method for forming conductive area by ionized metal plasma - Google Patents

Abstract

A method for forming conductive area by ionized metal plasma comprises: forming a trench in a substrate having a barrier layer; performing a directional deposition process to form conductive substance on the barrier layer and a bottom surface of the trench, the directional deposition process utilizing an ionized metal plasma technique; then, removing the conductive substance on the barrier layer; performing a silicidation process to make the conductive substance to react with the substrate, thereby forming a silicide on the bottom surface of the trench; and further removing the barrier layer after the silicidation process.

Description

4 523 6 V. Description of the invention (1) Field of the invention: The present invention relates to a method for manufacturing integrated circuits, in particular to a method for manufacturing wires by using ionized metal plasma. BACKGROUND OF THE INVENTION: Each component requires interconnections to exchange electrical signals between the components. In particular, high-efficiency integrated circuits have multiple layers of wires separated by dielectric layers. When the circuit's characteristic structure is reduced, the need to reduce the resistance associated with electrical connections or contact windows will become more important than ever. The higher the resistance, the slower the circuit operation speed is limited by the RC delay time. One way to solve this problem is to replace polycrystalline silicon with aluminum or aluminum alloy. Reducing the size of individual components can increase the integration of semiconductor integrated circuits. As the degree of integration of semiconductor elements increases, the area of each memory cell typically decreases. In order to reduce the area of the memory cell, several techniques have been introduced to improve the performance of the device, for example, by increasing the effective area of the memory cell capacitance to increase the capacitance of the memory cell. In order to increase the effective area of the memory cell capacitance, so-called stacked capacitors, trench capacitor structures, and combinations thereof have been developed. As component sizes shrink, the fabrication of integrated circuits also faces many challenges. Many components have wires that perform certain functions, such as bit lines and storage node access windows that are indispensable for the memory cells of dynamic random access memory cells. Therefore, it is necessary to reduce the design rules of the area and ensure sufficient processes.

4 52 8 6; V. Description of the invention (2) Error. The bit line of the dynamic random access memory cell usually includes a metal line that passes through the insulation layer and is connected to the active area. One method to reduce the area occupied by bit lines in dynamic random access memory is the embedded bit line concept. In an effort to solve the problems encountered by this technology, De n η si n proposed a buried bit 1 i ne (BBL) memory cell in U.S. Patent No. 5,250, 45 7, The bit lines are buried in an insulating region of a stacked memory cell. In addition, Park et al., Filed on November 3, 1995, and are entitled " Method of manufacturing buried bit line DRAM cel Γ, U.S. Patent No. 5,84 0, 5 91, disclose a formation in a trench Embedded bit line DRAM memory cell. A gate perpendicular to the bit line is formed on the substrate, a self-aligned bit line contact window is formed in an insulating layer to make contact between the sum electrode and the buried bit line; a self-aligned buried A contact window is formed in the insulating layer so that the source electrode is in contact with a storage electrode. Another method of manufacturing buried bit lines includes rounding-insulating layers and a substrate to form trenches in the substrate. A liner oxide layer is then formed on the surface of the trench, and a first conductive layer is formed on the insulating layer to cover the liner oxide layer and fill the trench. A portion of the first conductive layer is removed to expose a portion of the pad oxide layer. Next, the exposed pad oxide layer is removed to form a gap filling the second conductive layer along the trench on the insulating layer. For details of this method, please refer to U.S. Patent No. 5,882,97, filed July 10, 1998. This embedded bit line technology also works

Page 5 4 52 8 ο 5. Description of the invention (3) Other semiconductor components for dynamic random access memory outside the body, such as US Patent No. 6,048,76 5 by Wu, whose name is "Method of forming high" density buried bit line flash EEPROM memory cell with shallow trench floating gate ". For other previous techniques, please refer to US Patent No. 6,100,172, filed by IBM on October 29, 998. The invention discloses a novel embedded bit line, which can be used for semiconductor devices such as DRAM, FLASHA SRAM, and the like. Object and Summary of the Invention The object of the present invention is to form a conductive region in a trench by an ionized metal plasma layer. A substrate is etched to form a trench therein, and the substrate has a barrier layer. A conductive substance is then formed on the upper surface of the substrate and the bottom surface of the trench by an ionic metal plasma (IMP) technology. It must be noted that there is no conductive material on the side walls of the trench. For example, a chemical mechanical polishing method is used to remove the conductive material formed on the barrier layer to leave the conductive material below the trench. The conductive material is reacted with the substrate by a thermal process to form silicide at the lower portion of the trench. The next step is to remove the barrier layer by chemical mechanical polishing or a chemical solvent.

Page 6 4528 5. Description of the invention (4) Detailed description of the invention: The present invention relates to a method for manufacturing interconnecting conductors (such as buried bit lines). The invention is applicable to any element, such as dynamic random access memory, static random access memory, and flash memory. A method of making a lead in a trench in a substrate. The trench therefore has a side wall (which refers to a vertical surface) and a bottom surface (refers to a lower horizontal surface), and the substrate surface refers to an upper horizontal surface. The upper surface includes a barrier layer formed thereon. This method includes forming an ionized metal plasma layer on the upper horizontal surface and the lower horizontal flat surface. As shown below, please return to FIG. 1 to provide a substrate 2. The substrate 2 may be Shi Xi, Aluminized Gallium, and Germanium. For example, in one embodiment, a single crystal silicon substrate 2 with a crystal orientation < 1 0 0 > is used. The substrate 2 has one or more semiconductor elements therein. The wire of this component is not the subject of the present invention, but the component or its function is not much related to the present invention, so it is not annoying. Then, a barrier layer 4 (such as silicon oxide or silicon nitride) is formed on the substrate 2. The silicon oxide layer is typically formed by a thermal oxidation method in an oxygen-containing environment. In one embodiment, the silicon oxide layer is formed in an oxygen vapor environment at 800 to 110 degrees Celsius; or, the oxide layer may be formed by any suitable oxidizing composition and process. . The silicon nitride layer is deposited by any suitable process, such as low pressure chemical vapor deposition (L P C V D), electrical

45; 5. Description of the invention (5) ~~~~ Auxiliary chemical vapor deposition (p E c V D), high density plasma chemical vapor deposition (HDPCVD). The thickness of the silicon nitride layer is about 1000 to 2000 Angstroms. In a preferred embodiment, the reaction gas of the step of forming the silicon nitride layer includes SiH4, NH3, N2, N20, SiH2Cl2, NH3, and N20. Next, a pattern of the barrier layer is formed to define a trench region. Then, the substrate is etched by using the barrier layer 4 or a photoresist layer as an etch mask. A trench 6 is formed in this step. The substrate 2 can then be cleaned in a wet cleaning process. The trench 6 has a vertical plane and a horizontal plane. Similarly, the upper surface of the substrate also refers to the horizontal surface. Then, a conductive substance 8 is formed on the upper surface of the substrate 2 and the bottom surface of the trench 6. It must be noted that no conductive material 8 is formed on the sidewall of the trench 6. It is best to form the above-mentioned conductive material by ion metal plasma (Imp) technology. The IMP method has directional characteristics, and its deposits are formed only on the horizontal surface. The conductive substance 8 may be selected from the group consisting of aluminum, tungsten, platinum, and titanium. ”Ion Metal PUsma (IMP) " or " ion sputtering deposition means ion sputtering deposition method. It is best to use magnetron sputtering deposition method (where the magnet array is placed behind the target material). There is a high-density inductively coupled RF plasma between the cathode and the substrate supporting electrode. At least part of the sputtered ejection material reaches the surface of the substrate in the form of ions. For one of these technologies, please refer to US Patent No. No. 5,985,75 9 and its title is "Oxygen enhancement of ion metal p1asma (IMP) spu11er deposited barrier layers1.

Page 8 4 5 2 6 c. V. Description of the invention (6) Please refer to FIG. 2 'Remove the conductive substance 8 on the barrier layer 4 (for example, by chemical mechanical polishing method) to leave the conductive part on the lower part of the trench 6 Substance g. Referring to FIG. 3 ', the conductive material is reacted with the substrate 2 by a thermal process, thereby forming a metal silicide 10 at the lower part of the trench. As is well known to those skilled in the art, this metal silicide reduces the resistance value. … Please refer to FIG. 4, the next step is to remove the barrier layer 4 by chemical mechanical polishing or chemical solvent. The second embodiment is to perform the silicidation process before removing the material on the barrier layer 4 as shown in FIG. 5. In this next step, the barrier layer 4 can be directly removed after the petrochemical process to obtain the structure shown in FIG. 4. result. The first embodiment / For example, the second embodiment first performs a silicidation step. The difference is that the conductive material 8 on the barrier layer 4 is removed during the silicidation process, and then the barrier layer 4 is removed. The result. The above is only a preferred embodiment of the present invention, and its purpose is to ― the differences and similarities in the spirit and scope of the scope of patent application of the present invention = Gai Liang; $ Improved similar structure 'Therefore, what is described in the preferred embodiment of the present invention and what can be recognized is that other completed without departing from the spirit disclosed by the present invention ^' equivalent changes or modifications' should be included in the following patent application Fan Yuan ^, Zhi

Page 5 4 5286 Schematic illustration Schematic description: The preferred embodiment of the present invention will be explained in more detail in the following explanatory text with the following figures: Figure 1 is a cross-section of a semiconductor wafer. To illustrate the steps of forming an ionic metal plasma layer in the present invention; FIG. 2 is a cross-section of a semiconductor wafer to illustrate the steps of removing the ionic metal plasma layer on the barrier layer according to the present invention; FIG. 3 is a semiconductor wafer Fig. 4 is a cross-section of a semiconductor wafer to illustrate the steps of removing the barrier layer of the present invention; and Fig. 5 is a cross-section of a semiconductor wafer to illustrate the present invention. Invented the silicidation process before the ionic metal plasma layer. Substrate 2 Barrier layer 4 Ditch 6 Conductive substance 8

P. 10 4 Schematic illustration of metal silicide 1 0 (111 p. 11

Claims (1)

Δ 5286 5 VI. Scope of patent application Patent scope: 1. A method for manufacturing wires by using ionized metal plasma, the method includes at least the following steps: forming a trench in a substrate, and the substrate has a barrier thereon Layer; performing a directional deposition to form a conductive substance on the bottom surface of the barrier layer and the trench; removing the conductive substance from the barrier layer; and performing a silicidation process to react the conductive substance with the substrate to Formation—Metal silicide is on the bottom surface of the trench. 2. The method according to item 1 of the scope of patent application, further comprising removing the barrier layer after the silicidation process. 3. The method according to item 1 of the scope of patent application, wherein the directional deposition includes an ionized metal plasma technology. 4. The method according to item 1 of the scope of patent application, wherein the conductive material is removed by chemical mechanical polishing. 5. The method according to item 1 of the scope of patent application, wherein said barrier layer contains an oxide. 6. The method according to item 1 of the scope of patent application, wherein the above barrier layer package Page 12 ^ 5286 〇 6. Scope of Patent Application Contains nitrides. 7. The method according to item 1 of the scope of the patent application, wherein the conductive substance comprises Shao, He, Shi and Titanium. 8. A method for manufacturing a wire from an ionized metal plasma, the method includes at least the following steps: forming a trench in a substrate, the substrate having a barrier layer thereon; and performing a directional deposition to form a conductive substance on the substrate The barrier layer and one bottom surface of the trench; and a silicidation process is performed to react the conductive substance with the substrate to form a metal silicide on the bottom surface of the trench. The first layer of siege Fan obstructs the profit, except that the method described in item 9 and 8 of the procedure is also included, and it is also included in the silicidation 10 above. The method described in item 8 of the scope of patent application is further included in the above silicification. After the process, the conductive material on the barrier layer is removed. 11. The method according to item 10 of the scope of patent application, further comprising removing the barrier layer after removing the conductive substance on the barrier layer. 1 2. The method as described in item 10 of the scope of patent application, wherein the conductive material is removed by chemical mechanical polishing. Page 13 452865 VI. Scope of patent application 1 3. The method as described in item 8 of the scope of patent application, wherein the directional deposition includes an ionized metal electropolymerization technology. 14. The method according to item 8 of the scope of patent application, wherein the above barrier layer contains an oxide. 15. The method according to item 8 of the scope of patent application, wherein the barrier layer contains a nitride. 16. The method according to item 8 of the scope of patent application, wherein the conductive material comprises aluminum, tungsten, platinum, and titanium. Page 14