CN1883045A - 于接触形成中防止接触孔宽度增加的方法 - Google Patents

于接触形成中防止接触孔宽度增加的方法 Download PDF

Info

Publication number
CN1883045A
CN1883045A CNA2004800337772A CN200480033777A CN1883045A CN 1883045 A CN1883045 A CN 1883045A CN A2004800337772 A CNA2004800337772 A CN A2004800337772A CN 200480033777 A CN200480033777 A CN 200480033777A CN 1883045 A CN1883045 A CN 1883045A
Authority
CN
China
Prior art keywords
contact hole
layer
native oxide
contact
oxide layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2004800337772A
Other languages
English (en)
Chinese (zh)
Inventor
D·M·霍珀
H·木下
C·吴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN1883045A publication Critical patent/CN1883045A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
CNA2004800337772A 2003-11-08 2004-10-08 于接触形成中防止接触孔宽度增加的方法 Pending CN1883045A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/705,631 2003-11-08
US10/705,631 US7005387B2 (en) 2003-11-08 2003-11-08 Method for preventing an increase in contact hole width during contact formation

Publications (1)

Publication Number Publication Date
CN1883045A true CN1883045A (zh) 2006-12-20

Family

ID=34552414

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2004800337772A Pending CN1883045A (zh) 2003-11-08 2004-10-08 于接触形成中防止接触孔宽度增加的方法

Country Status (8)

Country Link
US (1) US7005387B2 (enExample)
JP (1) JP4662943B2 (enExample)
KR (1) KR101180977B1 (enExample)
CN (1) CN1883045A (enExample)
DE (1) DE112004002156T5 (enExample)
GB (1) GB2423635B (enExample)
TW (1) TWI359475B (enExample)
WO (1) WO2005048342A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080038910A1 (en) * 2006-08-10 2008-02-14 Advanced Micro Devices, Inc. Multiple lithography for reduced negative feature corner rounding
US20090050471A1 (en) * 2007-08-24 2009-02-26 Spansion Llc Process of forming an electronic device including depositing layers within openings
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
JP6494940B2 (ja) * 2013-07-25 2019-04-03 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ 異なるサイズのフィーチャへのボイドフリータングステン充填
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
KR102607331B1 (ko) * 2018-07-13 2023-11-29 에스케이하이닉스 주식회사 고종횡비 구조를 위한 갭필 방법 및 그를 이용한 반도체장치 제조 방법
DE112023002169T5 (de) 2023-01-05 2025-02-27 Fuji Electric Co., Ltd. Halbleitervorrichtung und Herstellungsverfahren dafür

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513411A (ja) * 1991-07-02 1993-01-22 Nec Corp 半導体装置の製造方法
JPH0661181A (ja) 1992-08-11 1994-03-04 Sony Corp バリアメタルの形成方法
JP3237917B2 (ja) * 1992-09-22 2001-12-10 沖電気工業株式会社 半導体素子の製造方法
JPH06349824A (ja) * 1993-06-10 1994-12-22 Toshiba Corp 半導体装置の製造方法
JPH09116009A (ja) * 1995-10-23 1997-05-02 Sony Corp 接続孔の形成方法
JPH09139358A (ja) * 1995-11-13 1997-05-27 Sony Corp 半導体装置の製造方法
US5985762A (en) * 1997-05-19 1999-11-16 International Business Machines Corporation Method of forming a self-aligned copper diffusion barrier in vias
TW388095B (en) * 1997-05-20 2000-04-21 United Microelectronics Corp Method for improving planarization of dielectric layer in interconnect metal process
JP3201318B2 (ja) * 1997-11-05 2001-08-20 日本電気株式会社 半導体装置の製造方法
US5994211A (en) * 1997-11-21 1999-11-30 Lsi Logic Corporation Method and composition for reducing gate oxide damage during RF sputter clean
US6303505B1 (en) * 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6511575B1 (en) * 1998-11-12 2003-01-28 Canon Kabushiki Kaisha Treatment apparatus and method utilizing negative hydrogen ion
KR100277086B1 (ko) * 1999-01-02 2000-12-15 윤종용 반도체 장치 및 그 제조 방법
JP4221859B2 (ja) * 1999-02-12 2009-02-12 株式会社デンソー 半導体装置の製造方法
US6348709B1 (en) * 1999-03-15 2002-02-19 Micron Technology, Inc. Electrical contact for high dielectric constant capacitors and method for fabricating the same
JP2000323571A (ja) * 1999-05-14 2000-11-24 Sony Corp 半導体装置の製造方法
KR100316721B1 (ko) * 2000-01-29 2001-12-12 윤종용 실리사이드막을 구비한 반도체소자의 제조방법
KR20010077743A (ko) * 2000-02-08 2001-08-20 박종섭 비트 라인 및 그 제조 방법
US6498091B1 (en) * 2000-11-01 2002-12-24 Applied Materials, Inc. Method of using a barrier sputter reactor to remove an underlying barrier layer
US6624066B2 (en) 2001-02-14 2003-09-23 Texas Instruments Incorporated Reliable interconnects with low via/contact resistance
US20030073304A1 (en) * 2001-10-16 2003-04-17 Applied Materials, Inc. Selective tungsten stud as copper diffusion barrier to silicon contact

Also Published As

Publication number Publication date
TW200524077A (en) 2005-07-16
US20050101148A1 (en) 2005-05-12
KR20060107763A (ko) 2006-10-16
KR101180977B1 (ko) 2012-09-07
US7005387B2 (en) 2006-02-28
WO2005048342A1 (en) 2005-05-26
JP2007511087A (ja) 2007-04-26
JP4662943B2 (ja) 2011-03-30
GB2423635A (en) 2006-08-30
GB0608285D0 (en) 2006-06-07
GB2423635B (en) 2007-05-30
DE112004002156T5 (de) 2006-09-14
TWI359475B (en) 2012-03-01

Similar Documents

Publication Publication Date Title
US20070284690A1 (en) Etch features with reduced line edge roughness
JP4417439B2 (ja) エッチング・ストップ層を利用する半導体装置構造とその方法
CN1617304A (zh) 在晶体管栅极结构上使用抗蚀刻衬里的方法和结构
US20070173050A1 (en) Semiconductor device and method of manufacturing the same
US20070066047A1 (en) Method of forming opening and contact
CN1883045A (zh) 于接触形成中防止接触孔宽度增加的方法
US6277736B1 (en) Method for forming gate
CN1567548A (zh) 形成阻障层的方法与结构
KR100912516B1 (ko) 다른 요소의 공정 중 메모리 셀의 액티브층 보호 방법
CN1266747C (zh) 有助于残留物去除的各向同性电阻器保护蚀刻
CN112530857B (zh) 半导体结构及其形成方法
US6767768B2 (en) Method for forming antifuse via structure
US7067417B2 (en) Methods of removing resistive remnants from contact holes using silicidation
CN1183581C (zh) 氮化钛层的制造方法
CN103117213A (zh) 金属栅极形成方法
JP2000150630A (ja) 半導体装置の製造方法及び半導体装置
KR100503312B1 (ko) 반도체 소자의 콘택 전극 제조 방법
CN1761040A (zh) 在表面上形成接触窗开口的方法
CN100394552C (zh) 接触窗开口的形成方法与半导体元件的制造方法
KR20080114228A (ko) 반도체 소자의 금속 배선 형성방법
US20070000860A1 (en) Method for fabricating semiconductor device
CN1567536A (zh) 金属硅化双层结构及其形成方法
KR100634258B1 (ko) 반도체 장치의 제조방법
KR100598187B1 (ko) 반도체 소자의 금속배선 형성 방법
CN1941294A (zh) 开口的形成方法以及接触窗的形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: GLOBALFOUNDRIES INC.

Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC.

Effective date: 20100730

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA STATE, USA TO: CAYMAN ISLANDS GRAND CAYMAN ISLAND

TA01 Transfer of patent application right

Effective date of registration: 20100730

Address after: Grand Cayman, Cayman Islands

Applicant after: Globalfoundries Semiconductor Inc.

Address before: American California

Applicant before: Advanced Micro Devices Inc.

C12 Rejection of a patent application after its publication
RJ01 Rejection of invention patent application after publication

Open date: 20061220