CN1617304A - 在晶体管栅极结构上使用抗蚀刻衬里的方法和结构 - Google Patents

在晶体管栅极结构上使用抗蚀刻衬里的方法和结构 Download PDF

Info

Publication number
CN1617304A
CN1617304A CNA2004100909735A CN200410090973A CN1617304A CN 1617304 A CN1617304 A CN 1617304A CN A2004100909735 A CNA2004100909735 A CN A2004100909735A CN 200410090973 A CN200410090973 A CN 200410090973A CN 1617304 A CN1617304 A CN 1617304A
Authority
CN
China
Prior art keywords
lining
substrate
gate stack
spacer
zone
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2004100909735A
Other languages
English (en)
Other versions
CN100452302C (zh
Inventor
H·Y·额
杨海宁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Core Usa Second LLC
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of CN1617304A publication Critical patent/CN1617304A/zh
Application granted granted Critical
Publication of CN100452302C publication Critical patent/CN100452302C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

一种覆盖晶体管栅极叠层的侧壁和沿晶体管栅极叠层的底部的衬底的一部分的抗蚀刻衬里。该衬里防止在栅极叠层的侧壁上形成可能引起电短路的硅化物，并在晶体管栅极叠层的底部的衬底中的源极和漏极区中确定硅化物形成的位置。该衬里还覆盖电阻器栅极叠层，防止在电阻器栅极叠层中或附近形成硅化物。

Description

在晶体管栅极结构上使用抗蚀刻衬里的方法和结构
技术领域
本发明一般涉及半导体器件及其制造方法，更具体地说涉及在晶体管栅极和/或电阻器栅极上使用抗蚀刻衬里的半导体器件的设计。
背景技术
在晶体管的栅极叠层的上表面上和源极/漏极区中形成硅化物所需的工艺期间，通常使用隔离物保护栅极叠层的侧壁。在形成硅化物之前，对晶片进行通常的预清洁工艺，以为硅化物形成准备栅极叠层的上表面和源极/漏极区。不幸地是，隔离物没有足够的抵抗力来对抗预清洁工艺，并且部分隔离物可能被不小心去掉。结果，暴露出部分栅极叠层的侧壁。然后，栅极叠层侧壁的暴露部分容易受到硅化物形成的影响。在栅极叠层的侧壁上形成硅化物可能导致在栅极叠层顶部的硅化物与栅极叠层底部的源极/漏极区中的硅化物之间电短路。由于半导体器件不断按比例缩小，并且栅极叠层顶部与源极/漏极区之间的距离也相应减小，所以由栅极叠层的侧壁上形成的硅化物引起的电短路的可能性也相应增加。
上述预清洁工艺还可能影响在晶体管附近形成的电阻器。为了保持所设计的电阻值，希望防止在电阻器栅极叠层中或周围形成硅化物。在预清洁工艺期间，保护电阻器栅极叠层侧壁的部分隔离物可能被去掉。与晶体管相同，电阻器栅极叠层的暴露部分容易受到硅化物形成的影响，导致电阻值降低。
因此，工业上需求形成能够克服上述问题的晶体管和/或电阻器栅极。
发明内容
本发明提供了一种在晶体管栅极叠层和电阻器栅极叠层上形成的抗蚀刻衬里，以解决上述问题。
本发明的第一方案提供了一种形成半导体器件的方法，包括：提供在衬底表面上具有栅极叠层的衬底；在栅极叠层上形成抗蚀刻衬里；在衬里上沿栅极叠层的侧壁形成隔离物；从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里，并在被隔离物覆盖的衬底和栅极叠层的区域中保留衬里；以及在没有被衬里覆盖的衬底和栅极叠层的区域中形成导电材料。
本发明的第二方案提供了一种形成半导体器件的方法，包括：提供在衬底表面上具有第一栅极叠层和第二栅极叠层的衬底；在第一和第二栅极叠层上形成衬里；在衬里上并沿第一和第二栅极叠层的侧壁形成隔离物；从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里；在第二栅极叠层上形成保护层；以及在没有被衬里覆盖的区域中形成导电材料。
本发明的第三方案提供了一种半导体器件，包括：在衬底上形成的栅极叠层；覆盖栅极叠层的侧壁和与栅极叠层相邻的部分衬底的抗蚀刻衬里；在衬里上沿栅极叠层的侧壁的隔离物；以及在栅极叠层的顶部区域中以及衬底的源极和漏极区域中的导电材料，其中源极和漏极区位于衬底上衬里的末端。
本发明的第四方案提供了一种半导体器件，包括：在衬底上形成的晶体管栅极叠层和电阻器栅极叠层；沿晶体管和电阻器栅极叠层的侧壁的第一隔离物；在晶体管和电阻器栅极叠层的第一隔离物上，并沿在晶体管和电阻器栅极叠层的底部的部分衬底的衬里，其中衬里沿衬底延伸到晶体管源极和漏极区的指定位置；在衬里上沿至少晶体管栅极叠层侧壁的隔离物；以及在晶体管栅极叠层的上表面中和晶体管源极和漏极区中的导电材料。
通过随后对本发明的实施例更详细的说明，本发明的上述和其它特征和优点将变得显而易见。
附图说明
下面参考附图详细说明本发明的实施例，其中相同的标号表示相同的元件，其中：
图1示出了根据第一实施例的部分半导体器件，其中在衬底上形成第一和第二栅极叠层；
图2示出了图1的衬底，其中沿栅极叠层的侧壁形成第一隔离物；
图3示出了图2的衬底，其中在衬底表面上形成衬里；
图4示出了图3的衬底，其中在衬里上并沿栅极叠层侧壁形成第二隔离物，并在衬底的表面上进行离子注入；
图5示出了图4的衬底，其中从衬底的表面去掉部分衬里；
图6示出了图5的衬底，其中在衬底的表面上淀积保护层，并在第二栅极叠层区上形成光致抗蚀剂层；
图7示出了从第一栅极叠层区的衬底表面上去掉保护层之后图6的衬底；
图8a示出了预清洁工艺之后图7的衬底；
图8b示出了在预清洁工艺之前图7的第一栅极叠层；
图8c示出了在预清洁工艺之后图7的第一栅极叠层；
图9示出了图8a的衬底，其中在衬底的选择区域中形成导电材料；
图10示出了根据第二实施例的部分半导体器件，其中在衬底上形成第一和第二栅极叠层，并在离子注入期间在第二栅极叠层区上形成光致抗蚀剂层；
图11示出了图10的衬底，其中从第一栅极叠层区中的衬底的表面去掉部分衬里；
图12示出了图11的衬底，其中在衬底的表面上淀积保护层，并在第二栅极叠层区上形成光致抗蚀剂层；
图13示出了从第一栅极叠层区中的衬底的表面去掉保护层之后图12的衬底；
图14示出了预清洁工艺之后图13的衬底；
图15示出了图14的衬底，其中在衬底的选择区域中形成导电材料；
图16示出了根据第三实施例的部分半导体器件，其中在衬底上形成第一和第二栅极叠层，并在衬底的表面形成衬里；
图17示出了在离子注入期间图16的衬底；
图18示出了图17的衬底，其中从衬底的表面去掉部分衬里；
图19示出了图18的衬底，其中在衬底的表面上淀积保护层，并在第二栅极叠层区上形成光致抗蚀剂层；
图20示出了从第一栅极叠层区中的衬底的表面去掉保护层之后图19的衬底；
图21示出了预清洁工艺之后图20的衬底；
图22示出了图21的衬底，其中在衬底的选择区域中形成导电材料；
图23示出了根据第四实施例的部分半导体器件，其中在衬底上形成第一和第二栅极叠层，在衬底的表面形成衬里，并沿栅极叠层的侧壁在衬里上形成第一隔离物；
图24示出了图23的衬底，具有在离子注入期间覆盖第二栅极叠层区的光致抗蚀剂层；
图25示出了图24的衬底，其中从衬底的表面去掉部分衬里；
图26示出了图25的衬底，其中在衬底的表面上淀积保护层，并在第二栅极叠层区上形成光致抗蚀剂层；
图27示出了从第一栅极叠层区中的衬底的表面去掉保护层之后图26的衬底；
图28示出了预清洁工艺之后图27的衬底；以及
图29示出了图28的衬底，其中在衬底的选择区域中形成导电材料。
具体实施方式
虽然将展示和详细说明本发明的某些实施例，但是应当理解，只要不脱离所附权利要求书的范围，可以进行各种变化和修改。本发明的范围并不限于构成元件的数量、材料、形状、相对排列等。虽然附图试图说明本发明，但是没有必要按比例绘制。
图1示出了半导体衬底10，其中如现有技术所公知在衬底10中形成STI12。衬底10包括硅或其它类似的材料。在STI12的两侧将形成有源区14、16。具体地说，将在第一有源区14中形成晶体管，并将在第二有源区16中形成电阻器。每个有源区14、16具有将衬底10与栅极叠层20、22分开的栅极介质层18。可以使用常规工艺形成包括多晶硅或其它类似材料的栅极叠层20、22。
如图2所示，沿栅极叠层20、22的侧壁形成第一隔离物24。第一隔离物24包括氧化物材料或其它类似材料。可以使用氧化工艺形成第一隔离物24，其中使用化学气相淀积(CVD)、等离子体增强化学气相淀积(PECVD)或其它类似工艺在侧壁26上淀积氧化物。然后使用反应离子蚀刻(RIE)或其它类似工艺蚀刻氧化物。所形成的第一隔离物24的厚度大约为50-200。
如图3所示，在衬底10的表面上形成衬里28，保形覆盖栅极叠层20、22和第一隔离物24。衬里28包括抗蚀刻材料，例如，具有高介电常数的材料(其中“高”是指介电常数(K)至少为7，并且在7-150的范围内)。例如，衬里28包括高K材料，例如，Al2O3、HfO2、Ta2O3或其它类似材料。或者，衬里28包括除如SiC的高K材料之外的抗蚀刻材料。所形成的衬里28的厚度范围大约为25-250。可以使用CVD、原子层淀积(ALD)、等离子体辅助CVD、溅射或其它类似工艺保形淀积衬里28。
如图4所示，在衬里28上沿栅极叠层20、22的侧壁形成第二隔离物30。第二隔离物30包括绝缘材料，例如，氮化物，例如，Si3N4或其它类似的绝缘材料。可以使用CVD、PECVD或其它类似工艺淀积第二隔离物30的材料。随后，可以使用RIE或其它类似工艺去掉过多的材料，从而形成第二隔离物30。所形成的第二隔离物30的厚度大约为200-800。
然后将离子32，例如Ge、Xe、Si等，注入到衬底10的表面中，以破坏衬里28的暴露区34、36，或者没有被第二隔离物30覆盖的区域34、36。具体地说，通过离子注入，有意破坏在栅极叠层20、22顶部上的衬里28的暴露区34和与栅极叠层20、22相邻的衬底10上的衬里28的暴露区36。随后，使用湿蚀刻化学去除在区34和36中的衬里28的破坏部分，如图5所示。
如图6所示，在衬底10的表面上保形淀积绝缘层38。然后使用常规工艺淀积、构图并蚀刻光致抗蚀剂40，以覆盖衬底10的电阻器区16，而保留衬底10的晶体管区14不被覆盖。进行蚀刻工艺，例如，RIE或其它类似工艺，从晶体管区14中的衬底10的表面去掉绝缘层38。去掉剩下的光致抗蚀剂40，留下在衬底10的电阻器区16上的保护层38，如图7所示。
使用“预清洁”工艺清洁衬底10的表面，以准备晶体管区14中的衬底10的表面，用于形成导电材料。例如，可以进行氢氟化物(HF)化学预清洁工艺。在预清洁工艺期间，由于缺乏抗蚀刻能力，第二隔离物30也被非有意地蚀刻掉一部分。结果，减小了第二隔离物30的厚度，如图8a-c所示。具体地说，图8b示出了在进行预清洁工艺之前第二隔离物30的厚度42。此时，第二隔离物30的厚度42使其大致延伸到与栅极叠层20的底部相邻的衬里28的末端44或沿栅极叠层20底部的衬底10的一部分。在预清洁工艺之后，减小了第二隔离物30的厚度46(图8c)，从而第二隔离物30没有延伸到与栅极叠层20的底部相邻的衬里28的末端44或沿栅极叠层20底部的衬底10的一部分。在本实施例中，在电阻器栅极叠层22上的第二隔离物30不受预清洁影响，因为栅极叠层22和隔离物24、30受层38保护。
如图9所示，在晶体管栅极叠层20的顶部区34上和晶体管的源极/漏极区50中形成导电材料48，例如，硅化物或其它类似的材料。通过使用PVD、CVD、溅射或其它类似的工艺在衬底10的表面上均匀的淀积一层难熔金属，例如钴或钛，形成导电材料48。然后，例如暴露在700℃的温度下大约30秒，退火金属。在退火工艺期间，金属扩散到硅的暴露区域中，形成了硅化物。随后，化学去除未反应的钴金属。
应当注意，衬里28限定或确定了相对于晶体管栅极叠层20在哪里形成导电材料48。如果没有使用衬里28，则在源极/漏极区50中形成的导电材料48将更靠近栅极叠层20的底部，因为在导电材料48形成之前进行的预清洁工艺减小了第二隔离物30的厚度46(参考图8c)。衬里28覆盖在区域52(在预清洁工艺之前最初被第二隔离物30覆盖的区域)中的衬底10中的硅，从而防止在区域52中形成导电材料48。如果所形成的导电材料48太靠近栅极叠层20的底部，则在晶体管栅极叠层20的顶部区域34上的导电材料48与在晶体管栅极叠层20的源极/漏极区50中的导电材料48之间电短路的可能性更大。
另外，衬里28防止在预清洁工艺期间从栅极叠层20、22的侧壁上去掉第一隔离物24。因为在第一隔离物24中没有形成破口，所以栅极叠层20、22的侧壁不会受导电材料48形成的影响。如在相关技术中所说明，在晶体管栅极叠层20的侧壁26上形成的导电材料48增加了在栅极叠层20的顶部区域上的导电材料48与在源极/漏极区50中的导电材料48之间电短路的可能性。而且，在电阻器栅极叠层22的侧壁26上形成的导电材料48降低了电阻器的电阻值。
在图10-15中示出了第二实施例。在本实施例中，没有去掉在电阻器栅极叠层22的顶部区域34上的衬里28以及与电阻器栅极叠层22相邻的区域36中的衬里28。具体地说，在根据第一实施例(图1-4)在衬里28上沿晶体管和电阻器栅极叠层20、22的侧壁26形成第二隔离物30之后，在衬底10上淀积掩膜层或光致抗蚀剂层54。如图10所示，构图并蚀刻光致抗蚀剂层54，以暴露衬底10的晶体管区14。如上所述，注入的离子32将只破坏在晶体管区14中的衬里28的暴露区34、36，而不破坏在电阻器区16中的衬里28。
随后，进行湿蚀刻，以去掉在区域34和36中衬里28的破坏部分，并去掉光致抗蚀剂54，如图11所示。如在第一实施例中所述，在衬底10的表面上保形淀积保护层38(图12)。然后使用常规工艺淀积、构图并蚀刻光致抗蚀剂40，以覆盖衬底10的电阻器区16，而保留衬底10的晶体管区14不被覆盖(图12)。进行蚀刻工艺，例如，RIE或其它类似的工艺，从晶体管区14中的衬底10的表面上去掉保护层38，如图13所示。还去掉剩余的光致抗蚀剂40，留下衬底10的电阻器区16上的保护层38(图13)。
随后，进行预清洁工艺，以准备晶体管区14中的衬底10的表面，用于形成导电材料48。如上所述，在预清洁工艺期间，第二隔离物30的厚度减小(图14)。在预清洁工艺期间，沿电阻器栅极叠层22的侧壁的第二隔离物30受层38保护。另外，第一隔离物24和电阻器栅极叠层22不受预清洁的影响，因为栅极叠层22和第一隔离物24受衬里28保护。
然后，在晶体管栅极叠层20的顶部区34上和晶体管的源极/漏极区50中形成导电材料48(图15)。但是，电阻器区16没有形成导电材料48，因为覆盖电阻器区16的整个表面的衬里28确保在导电材料48预清洁工艺期间，在隔离物24、30或保护层38中没有破口。
在图16-22中示出了第三实施例。不是沿晶体管栅极叠层20和电阻器栅极叠层22的侧壁26形成第一隔离物24，而是在栅极叠层20、22上直接形成衬里28，如图16所示。随后，在衬里28上沿栅极叠层20、22的侧壁26形成隔离物30，如图17所示。
然后，将离子32注入衬底10的表面，以破坏衬里28的暴露部分，如图17所示。如在第一实施例中所述，通过离子注入有意破坏衬里28的暴露区域。然后，使用湿蚀刻化学去除衬里28的破坏部分，如图18所示。
如图19所示，在衬底10的表面上保形淀积层38。然后使用常规工艺淀积、构图并蚀刻光致抗蚀剂40，以覆盖衬底10的电阻器区16，而保留衬底10的晶体管区14不被覆盖。蚀刻工艺从晶体管区14中的衬底10的表面上去掉层38。去掉剩余的光致抗蚀剂40，留下衬底10的电阻器区16上的保护层38，如图20所示。
进行预清洁工艺，以准备晶体管区14中的衬底10的表面，用于形成导电材料48。如在第一实施例中所述，在预清洁工艺期间，蚀刻第二隔离物30，从而减小第二隔离物30的厚度，如图21所示。如在第一实施例中所述，并如图22所示，在晶体管栅极叠层20的顶部区34上和晶体管的源极/漏极区50中形成导电材料48。
第四实施例组合了第二和第三实施例的一部分，并在图16和23-29中示出。与上述第三实施例相同，在栅极叠层20、22上直接形成衬里28，而不形成第一隔离物24，如图16所示。随后，在衬里28上沿栅极叠层20、22的侧壁26形成隔离物30，如图23所示。然后，淀积、构图和蚀刻光致抗蚀剂层54，如在第二实施例中所述，从而保护衬底10的电阻器区16，并暴露衬底10的晶体管区14，如图24所示。
然后，将离子32注入衬底10的表面，以破坏衬里28的暴露区域34、36，如图24所示。如在第一实施例中所述，通过离子注入有意破坏衬里28的暴露区域34、36。但是，光致抗蚀剂层54防止电阻器区16暴露在离子32下，从而保护在电阻器区16中的衬里28不被破坏，并最终防止被去掉。在离子32注入之后，去掉光致抗蚀剂层54，然后使用湿蚀刻化学去除衬里28的破坏部分，如图25所示。
如图26所示，在衬底10的表面上保形淀积层38。然后，淀积、构图并蚀刻光致抗蚀剂40，以覆盖衬底10的电阻器区16，而保留衬底10的晶体管区14不被覆盖。蚀刻工艺从晶体管区14中的衬底10的表面上去掉层38。去掉剩余的光致抗蚀剂40，留下衬底10的电阻器区16上的保护层38，如图27所示。
进行预清洁工艺，以准备晶体管区14中的衬底10的表面，用于形成导电材料48。如在第一实施例中所述，在预清洁工艺期间，蚀刻第二隔离物30，从而减小第二隔离物30的厚度(图28)。如在第一实施例中所述，并如图29所示，在晶体管栅极叠层20的顶部区34上和晶体管的源极/漏极区50中形成导电材料48。

Claims (31)

1.一种形成半导体器件的方法，包括：
提供在衬底表面上具有栅极叠层的衬底；
在栅极叠层上形成抗蚀刻衬里；
在衬里上沿栅极叠层的侧壁形成隔离物；
从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里，并在被隔离物覆盖的衬底和栅极叠层的区域中保留衬里；以及
在没有被衬里覆盖的衬底和栅极叠层的区域中形成导电材料。
2.根据权利要求1的方法，还包括在栅极叠层上形成衬里之前：
在衬底的表面上提供第二栅极叠层。
3.根据权利要求2的方法，还包括：
在第二栅极叠层上形成衬里；以及
在衬里上沿第二栅极叠层的侧壁形成隔离物。
4.根据权利要求3的方法，还包括在从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里，并在被隔离物覆盖的衬底和栅极叠层的区域中保留衬里之前：
在衬里和第二栅极叠层的隔离物上淀积光致抗蚀剂层，以防止从第二栅极叠层上去掉衬里。
5.根据权利要求3的方法，还包括在从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里，并在被隔离物覆盖的衬底和栅极叠层的区域中保留衬里之后：
在形成导电材料之前在覆盖第二栅极叠层的衬底的表面上形成绝缘层。
6.根据权利要求2的方法，还包括在栅极叠层上形成衬里之前：
沿第一和第二栅极叠层的侧壁形成第一隔离物。
7.根据权利要求2的方法，其中栅极叠层包括晶体管栅极叠层，第二栅极叠层包括电阻器栅极叠层。
8.根据权利要求1的方法，其中衬里包括选自如下的材料：Al2O3、HfO2和Ta2O3。
9.根据权利要求1的方法，其中衬里包括SiC。
10.根据权利要求1的方法，还包括在去掉衬里的衬底和栅极叠层的区域中形成导电材料之前：
在衬底的表面上进行预清洁工艺。
11.根据权利要求1的方法，其中衬里包括介电常数的范围为约7-150的材料。
12.根据权利要求1的方法，还包括在形成导电材料期间：
在衬底中形成源极和漏极区，其中通过从没有被隔离物覆盖的区域去掉衬里产生的衬里的末端确定源极和漏极区的位置。
13.一种形成半导体器件的方法，包括：
提供在衬底表面上具有第一栅极叠层和第二栅极叠层的衬底；
在第一和第二栅极叠层上形成衬里；
在衬里上并沿第一和第二栅极叠层的侧壁形成隔离物；
从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里；
在第二栅极叠层上形成保护层；以及
在没有被衬里覆盖的区域中形成导电材料。
14.根据权利要求13的方法，还包括在第一和第二栅极叠层上形成衬里之前：
沿第一和第二栅极叠层的侧壁形成第一隔离物。
15.根据权利要求13的方法，还包括在从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里之前：
在衬里和第二栅极叠层的隔离物上淀积光致抗蚀剂层，以防止从第二栅极叠层上去掉衬里。
16.根据权利要求13的方法，还包括在形成导电材料之前：
在第二栅极叠层上形成绝缘层；以及
在衬底上进行预清洁工艺。
17.根据权利要求13的方法，其中衬里包括抗蚀刻材料。
18.根据权利要求13的方法，其中衬里包括选自如下的材料：Al2O3、HfO2和Ta2O3。
19.根据权利要求13的方法，其中衬里包括SiC。
20.根据权利要求13的方法，其中衬里包括介电常数的范围为约7-150的材料。
21.根据权利要求13的方法，还包括在形成导电材料期间：
在衬底中形成源极和漏极区，其中通过从没有被隔离物覆盖的区域去掉衬里产生的衬里的末端确定源极和漏极区的位置。
22.一种半导体器件，包括：
在衬底上形成的栅极叠层；
覆盖栅极叠层的侧壁和与栅极叠层相邻的部分衬底的抗蚀刻衬里；
在衬里上沿栅极叠层的侧壁的隔离物；以及
在栅极叠层的顶部区域中以及衬底的源极和漏极区域中的导电材料，其中源极和漏极区位于衬底上衬里的末端。
23.根据权利要求22的半导体器件，其中衬里包括介电常数的范围为约7-150的材料。
24.根据权利要求22的半导体器件，其中衬里包括选自如下的材料：Al2O3、HfO2和Ta2O3。
25.根据权利要求22的半导体器件，其中衬里包括SiC。
26.一种半导体器件，包括：
在衬底上形成的晶体管栅极叠层和电阻器栅极叠层；
沿晶体管和电阻器栅极叠层的侧壁的第一隔离物；
在晶体管和电阻器栅极叠层的第一隔离物上，并沿在晶体管和电阻器栅极叠层的底部的部分衬底的衬里，其中衬里沿衬底延伸到晶体管源极和漏极区的指定位置；
在衬里上沿至少晶体管栅极叠层侧壁的隔离物；以及
在晶体管栅极叠层的上表面中和晶体管源极和漏极区中的导电材料。
27.根据权利要求26的半导体器件，还包括：
覆盖电阻器栅极叠层和在电阻器栅极叠层的底部的部分衬底的保护层。
28.根据权利要求26的半导体器件，其中衬里覆盖整个电阻器栅极叠层和在电阻器栅极叠层的底部的部分衬底。
29.根据权利要求26的半导体器件，其中衬里包括介电常数的范围为约7-150的材料。
30.根据权利要求26的半导体器件，其中衬里包括选自如下的材料：Al2O3、HfO2和Ta2O3。
31.根据权利要求26的半导体器件，其中衬里包括SiC。
CNB2004100909735A 2003-11-13 2004-11-11 在晶体管栅极结构上使用抗蚀刻衬里的方法和结构 Expired - Fee Related CN100452302C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/713,227 US7064027B2 (en) 2003-11-13 2003-11-13 Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
US10/713,227 2003-11-13

Publications (2)

Publication Number Publication Date
CN1617304A true CN1617304A (zh) 2005-05-18
CN100452302C CN100452302C (zh) 2009-01-14

Family

ID=34573664

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004100909735A Expired - Fee Related CN100452302C (zh) 2003-11-13 2004-11-11 在晶体管栅极结构上使用抗蚀刻衬里的方法和结构

Country Status (4)

Country Link
US (3) US7064027B2 (zh)
JP (1) JP4587774B2 (zh)
KR (1) KR100562234B1 (zh)
CN (1) CN100452302C (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447455B (zh) * 2007-11-30 2011-06-22 东部高科股份有限公司 制造lcd驱动ic的方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7064027B2 (en) * 2003-11-13 2006-06-20 International Business Machines Corporation Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
JP4069867B2 (ja) * 2004-01-05 2008-04-02 セイコーエプソン株式会社 部材の接合方法
US8535383B2 (en) * 2004-01-12 2013-09-17 DePuy Synthes Products, LLC Systems and methods for compartmental replacement in a knee
US20060157750A1 (en) * 2005-01-20 2006-07-20 Samsung Electronics Co., Ltd. Semiconductor device having etch-resistant L-shaped spacer and fabrication method thereof
US7790561B2 (en) * 2005-07-01 2010-09-07 Texas Instruments Incorporated Gate sidewall spacer and method of manufacture therefor
US7399690B2 (en) 2005-11-08 2008-07-15 Infineon Technologies Ag Methods of fabricating semiconductor devices and structures thereof
US20070224808A1 (en) * 2006-03-23 2007-09-27 Taiwan Semiconductor Manufacturing Company, Ltd. Silicided gates for CMOS devices
US7361539B2 (en) * 2006-05-16 2008-04-22 International Business Machines Corporation Dual stress liner
US7768041B2 (en) * 2006-06-21 2010-08-03 International Business Machines Corporation Multiple conduction state devices having differently stressed liners
JP4716938B2 (ja) * 2006-06-30 2011-07-06 富士通セミコンダクター株式会社 半導体装置の製造方法
US7696036B2 (en) * 2007-06-14 2010-04-13 International Business Machines Corporation CMOS transistors with differential oxygen content high-k dielectrics
KR101413044B1 (ko) * 2008-03-10 2014-06-30 삼성전자주식회사 금속 실리사이드막을 포함하는 반도체 장치 및 그 제조방법
JP2011023498A (ja) * 2009-07-15 2011-02-03 Panasonic Corp 半導体装置及びその製造方法
US9496359B2 (en) 2011-03-28 2016-11-15 Texas Instruments Incorporated Integrated circuit having chemically modified spacer surface
US9087917B2 (en) * 2013-09-10 2015-07-21 Texas Instruments Incorporated Inner L-spacer for replacement gate flow
US10868027B2 (en) 2018-07-13 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for preventing silicide contamination during the manufacture of micro-processors with embedded flash memory
US10868142B2 (en) * 2018-10-31 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Gate spacer structure and method of forming same
CN113539805A (zh) * 2020-04-13 2021-10-22 华邦电子股份有限公司 半导体结构及其形成方法

Family Cites Families (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04152535A (ja) 1990-10-16 1992-05-26 Sanyo Electric Co Ltd 半導体装置
GB9127093D0 (en) 1991-02-26 1992-02-19 Samsung Electronics Co Ltd Field-effect transistor
JPH05211163A (ja) 1991-11-19 1993-08-20 Hitachi Ltd 半導体装置およびその製造方法
EP0550255B1 (en) * 1991-12-31 1998-03-11 STMicroelectronics, Inc. Transistor spacer structure
JPH07161991A (ja) * 1993-12-10 1995-06-23 Ricoh Co Ltd 半導体装置の製造方法
US5616935A (en) * 1994-02-08 1997-04-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor integrated circuit having N-channel and P-channel transistors
US5525552A (en) * 1995-06-08 1996-06-11 Taiwan Semiconductor Manufacturing Company Method for fabricating a MOSFET device with a buried contact
US5633781A (en) * 1995-12-22 1997-05-27 International Business Machines Corporation Isolated sidewall capacitor having a compound plate electrode
JPH09312395A (ja) * 1996-05-23 1997-12-02 Toshiba Corp 半導体装置の製造方法
US5747373A (en) * 1996-09-24 1998-05-05 Taiwan Semiconductor Manufacturing Company Ltd. Nitride-oxide sidewall spacer for salicide formation
US5908315A (en) * 1997-08-18 1999-06-01 Advanced Micro Devices, Inc. Method for forming a test structure to determine the effect of LDD length upon transistor performance
US6207485B1 (en) * 1998-01-05 2001-03-27 Advanced Micro Devices Integration of high K spacers for dual gate oxide channel fabrication technique
US6127235A (en) * 1998-01-05 2000-10-03 Advanced Micro Devices Method for making asymmetrical gate oxide thickness in channel MOSFET region
TW387151B (en) * 1998-02-07 2000-04-11 United Microelectronics Corp Field effect transistor structure of integrated circuit and the manufacturing method thereof
US5904517A (en) * 1998-07-08 1999-05-18 Advanced Micro Devices, Inc. Ultra thin high K spacer material for use in transistor fabrication
US6271563B1 (en) * 1998-07-27 2001-08-07 Advanced Micro Devices, Inc. MOS transistor with high-K spacer designed for ultra-large-scale integration
US6008095A (en) * 1998-08-07 1999-12-28 Advanced Micro Devices, Inc. Process for formation of isolation trenches with high-K gate dielectrics
US6348389B1 (en) * 1999-03-11 2002-02-19 Taiwan Semiconductor Manufacturing Company Method of forming and etching a resist protect oxide layer including end-point etch
US6194748B1 (en) * 1999-05-03 2001-02-27 Advanced Micro Devices, Inc. MOSFET with suppressed gate-edge fringing field effect
US6593632B1 (en) * 1999-08-17 2003-07-15 Advanced Micro Devices, Inc. Interconnect methodology employing a low dielectric constant etch stop layer
US6512273B1 (en) * 2000-01-28 2003-01-28 Advanced Micro Devices, Inc. Method and structure for improving hot carrier immunity for devices with very shallow junctions
US6271094B1 (en) * 2000-02-14 2001-08-07 International Business Machines Corporation Method of making MOSFET with high dielectric constant gate insulator and minimum overlap capacitance
CN100543999C (zh) * 2000-09-01 2009-09-23 精工电子有限公司 Cmos半导体器件及其制造方法
JP3544535B2 (ja) * 2000-09-18 2004-07-21 松下電器産業株式会社 半導体装置及びその製造方法
KR100699813B1 (ko) * 2000-09-27 2007-03-27 삼성전자주식회사 반도체 메모리 소자의 제조 방법
JP4897146B2 (ja) * 2001-03-02 2012-03-14 ルネサスエレクトロニクス株式会社 半導体装置の製造方法、および半導体装置
JP4628644B2 (ja) * 2001-10-04 2011-02-09 富士通セミコンダクター株式会社 半導体装置の製造方法
US6680233B2 (en) 2001-10-09 2004-01-20 Advanced Micro Devices, Inc. Semiconductor device formed with disposable spacer and liner using high-K material and method of fabrication
US6586332B1 (en) * 2001-10-16 2003-07-01 Lsi Logic Corporation Deep submicron silicide blocking
TW510048B (en) * 2001-11-16 2002-11-11 Macronix Int Co Ltd Manufacturing method of non-volatile memory
CN1420552A (zh) * 2001-11-21 2003-05-28 旺宏电子股份有限公司 氮化硅只读存储器的结构与制造方法
US6753242B2 (en) * 2002-03-19 2004-06-22 Motorola, Inc. Integrated circuit device and method therefor
US6613637B1 (en) * 2002-05-31 2003-09-02 Lsi Logic Corporation Composite spacer scheme with low overlapped parasitic capacitance
US6743669B1 (en) * 2002-06-05 2004-06-01 Lsi Logic Corporation Method of reducing leakage using Si3N4 or SiON block dielectric films
US6657267B1 (en) * 2002-06-06 2003-12-02 Advanced Micro Devices, Inc. Semiconductor device and fabrication technique using a high-K liner for spacer etch stop
US6894353B2 (en) * 2002-07-31 2005-05-17 Freescale Semiconductor, Inc. Capped dual metal gate transistors for CMOS process and method for making the same
US6815355B2 (en) * 2002-10-09 2004-11-09 Chartered Semiconductor Manufacturing Ltd. Method of integrating L-shaped spacers in a high performance CMOS process via use of an oxide-nitride-doped oxide spacer
US6943077B2 (en) * 2003-04-07 2005-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. Selective spacer layer deposition method for forming spacers with different widths
US6891192B2 (en) * 2003-08-04 2005-05-10 International Business Machines Corporation Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions
US6906360B2 (en) * 2003-09-10 2005-06-14 International Business Machines Corporation Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regions
US6908822B2 (en) * 2003-09-15 2005-06-21 Freescale Semiconductor, Inc. Semiconductor device having an insulating layer and method for forming
US7064027B2 (en) * 2003-11-13 2006-06-20 International Business Machines Corporation Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
US7190033B2 (en) * 2004-04-15 2007-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS device and method of manufacture
US20060079046A1 (en) * 2004-10-12 2006-04-13 International Business Machines Corporation Method and structure for improving cmos device reliability using combinations of insulating materials
US7494858B2 (en) * 2005-06-30 2009-02-24 Intel Corporation Transistor with improved tip profile and method of manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101447455B (zh) * 2007-11-30 2011-06-22 东部高科股份有限公司 制造lcd驱动ic的方法

Also Published As

Publication number Publication date
US20080036017A1 (en) 2008-02-14
KR100562234B1 (ko) 2006-03-22
US20050104095A1 (en) 2005-05-19
JP4587774B2 (ja) 2010-11-24
KR20050046536A (ko) 2005-05-18
US7064027B2 (en) 2006-06-20
CN100452302C (zh) 2009-01-14
JP2005150713A (ja) 2005-06-09
US7307323B2 (en) 2007-12-11
US20060145275A1 (en) 2006-07-06

Similar Documents

Publication Publication Date Title
CN1617304A (zh) 在晶体管栅极结构上使用抗蚀刻衬里的方法和结构
CN1309052C (zh) 用于制造垂直dram中的钨/多晶硅字线结构的方法及由此制造的器件
CN1292473C (zh) 混合平面和FinFET CMOS器件
CN1177357C (zh) 具有最小覆盖电容的金属氧化物半导体场效应晶体管
CN1902740A (zh) 利于高产量并包括蚀刻终止层和/或应力膜的置换栅流程
CN1670964A (zh) 金属氧化物半导体场效应晶体管及其制造方法
CN1855548A (zh) 半导体存储器件及其制造方法
CN1725515A (zh) 具有重叠栅电极的半导体器件及其制造方法
CN1280903C (zh) 具有伪结构的半导体器件
CN1763970A (zh) 薄型绝缘半导体之绝缘间隙壁
CN1992275A (zh) 具有金属和多晶硅栅电极的高性能电路及其制造方法
CN1790740A (zh) 半导体器件及用于形成栅极结构的方法
CN101043055A (zh) 制造场效应晶体管的方法以及半导体结构
CN1499646A (zh) 半导体器件和半导体器件的制造方法
CN100590815C (zh) 半导体器件的制造方法
CN100517618C (zh) 半导体器件及其制造方法
US7393746B2 (en) Post-silicide spacer removal
CN1523675A (zh) 半导体器件及其制造方法
WO2006032300A1 (en) Semiconductor device and method of forming the same
CN1182583C (zh) 具有增大栅耦合电容的集成电路
CN1286163C (zh) 半导体存储器件及其制造方法
CN1855392A (zh) 半导体元件的制造方法及调整元件沟道区晶格距离的方法
CN113972265B (zh) 一种改善带场板的ldmos制程工艺的方法
CN1231949C (zh) 形成栅极结构的方法、自对准接触孔结构及其形成方法
CN1741283A (zh) 半导体装置及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20171103

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171103

Address after: American New York

Patentee after: Core USA second LLC

Address before: American New York

Patentee before: International Business Machines Corp.

CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090114

Termination date: 20181111