CN100452302C - 在晶体管栅极结构上使用抗蚀刻衬里的方法和结构 - Google Patents

在晶体管栅极结构上使用抗蚀刻衬里的方法和结构 Download PDF

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CN100452302C
CN100452302C CNB2004100909735A CN200410090973A CN100452302C CN 100452302 C CN100452302 C CN 100452302C CN B2004100909735 A CNB2004100909735 A CN B2004100909735A CN 200410090973 A CN200410090973 A CN 200410090973A CN 100452302 C CN100452302 C CN 100452302C
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H·Y·额
杨海宁
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GlobalFoundries Inc
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Abstract

一种覆盖晶体管栅极叠层的侧壁和沿晶体管栅极叠层的底部的衬底的一部分的抗蚀刻衬里。该衬里防止在栅极叠层的侧壁上形成可能引起电短路的硅化物，并在晶体管栅极叠层的底部的衬底中的源极和漏极区中确定硅化物形成的位置。该衬里还覆盖电阻器栅极叠层，防止在电阻器栅极叠层中或附近形成硅化物。

Description

在晶体管栅极结构上使用抗蚀刻衬里的方法和结构
技术领域
本发明一般涉及半导体器件及其制造方法，更具体地说涉及在晶体管栅极和/或电阻器栅极上使用抗蚀刻衬里的半导体器件的设计。
背景技术
在晶体管的栅极叠层的上表面上和源极/漏极区中形成硅化物所需的工艺期间，通常使用隔离物保护栅极叠层的侧壁。在形成硅化物之前，对晶片进行通常的预清洁工艺，以为硅化物形成准备栅极叠层的上表面和源极/漏极区。不幸地是，隔离物没有足够的抵抗力来对抗预清洁工艺，并且部分隔离物可能被不小心去掉。结果，暴露出部分栅极叠层的侧壁。然后，栅极叠层侧壁的暴露部分容易受到硅化物形成的影响。在栅极叠层的侧壁上形成硅化物可能导致在栅极叠层顶部的硅化物与栅极叠层底部的源极/漏极区中的硅化物之间电短路。由于半导体器件不断按比例缩小，并且栅极叠层顶部与源极/漏极区之间的距离也相应减小，所以由栅极叠层的侧壁上形成的硅化物引起的电短路的可能性也相应增加。
上述预清洁工艺还可能影响在晶体管附近形成的电阻器。为了保持所设计的电阻值，希望防止在电阻器栅极叠层中或周围形成硅化物。在预清洁工艺期间，保护电阻器栅极叠层侧壁的部分隔离物可能被去掉。与晶体管相同，电阻器栅极叠层的暴露部分容易受到硅化物形成的影响，导致电阻值降低。
因此，工业上需求形成能够克服上述问题的晶体管和/或电阻器栅极。
发明内容
本发明提供了一种在晶体管栅极叠层和电阻器栅极叠层上形成的抗蚀刻衬里，以解决上述问题。
本发明的第一方案提供了一种形成半导体器件的方法，包括：提供在衬底表面上具有栅极叠层的衬底；覆盖栅极叠层形成衬里，其中衬里选自Al2O3、HfO2或Ta2O3；在衬里上沿栅极叠层的侧壁形成隔离物；从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里，并在被隔离物覆盖的衬底和栅极叠层的区域中保留衬里；执行预清洁工艺以蚀刻未被衬里覆盖的衬底的表面；在没有被衬里覆盖的衬底和栅极叠层的区域中形成导电材料，其中在衬底中形成源极和漏极区，其中通过从没有被隔离物覆盖的区域去掉衬里产生的衬里的末端确定源极和漏极区导电材料的位置。
本发明的第二方案提供了一种形成半导体器件的方法，包括：一种形成半导体器件的方法，包括：提供在衬底表面上具有第一栅极叠层和第二栅极叠层的衬底；覆盖第一和第二栅极叠层形成衬里，其中衬里选自Al2O3、HfO2或Ta2O3；在衬里上并沿第一和第二栅极叠层的侧壁形成隔离物；从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里；在第二栅极叠层上形成保护层；以及在没有被衬里覆盖的区域中形成导电材料，其中在衬底中形成源极和漏极区，其中通过从没有被隔离物覆盖的区域去掉衬里产生的衬里的末端确定源极和漏极区导电材料的位置。
本发明的第三方案提供了一种半导体器件，包括：在衬底上形成的栅极叠层；覆盖棚极叠层的侧壁和与栅极叠层相邻的部分衬底的衬里，其中衬里选自Al2O3、HfO2或Ta2O3；在衬里上沿栅极叠层的侧壁的隔离物；以及在棚极叠层的顶部区域中以及衬底的源极和漏极区域中的导电材料，其中源极和漏极区导电材料的位置由位于衬底上衬里的末端确定。
本发明的第四方案提供了一种半导体器件，包括：在衬底上形成的晶体管栅极叠层和电阻器栅极叠层；沿晶体管和电阻器栅极叠层的侧壁的第一隔离物；在晶体管和电阻器栅极叠层的第一隔离物上，并沿在晶体管和电阻器栅极叠层的底部的部分衬底的衬里，其中衬里选自Al2O3、HfO2或Ta2O3并且沿衬底向晶体管源极和漏极区延伸；在衬里上沿至少晶体管栅极叠层侧壁的隔离物；以及在晶体管栅极叠层的上表面中和晶体管源极和漏极区中的导电材料，其中源极和漏极区导电材料的位置由位于衬底上衬里的末端确定。
通过随后对本发明的实施例更详细的说明，本发明的上述和其它特征和优点将变得显而易见。
附图说明
下面参考附图详细说明本发明的实施例，其中相同的标号表示相同的元件，其中：
图1示出了根据第一实施例的部分半导体器件，其中在衬底上形成第一和第二栅极叠层；
图2示出了图1的衬底，其中沿栅极叠层的侧壁形成第一隔离物；
图3示出了图2的衬底，其中在衬底表面上形成衬里；
图4示出了图3的衬底，其中在衬里上并沿栅极叠层侧壁形成第二隔离物，并在衬底的表面上进行离子注入；
图5示出了图4的衬底，其中从衬底的表面去掉部分衬里；
图6示出了图5的衬底，其中在衬底的表面上淀积保护层，并在第二栅极叠层区上形成光致抗蚀剂层；
图7示出了从第一栅极叠层区的衬底表面上去掉保护层之后图6的衬底；
图8a示出了预清洁工艺之后图7的衬底；
图8b示出了在预清洁工艺之前图7的第一栅极叠层；
图8c示出了在预清洁工艺之后图7的第一栅极叠层；
图9示出了图8a的衬底，其中在衬底的选择区域中形成导电材料；
图10示出了根据第二实施例的部分半导体器件，其中在衬底上形成第一和第二栅极叠层，并在离子注入期间在第二栅极叠层区上形成光致抗蚀剂层；
图11示出了图10的衬底，其中从第一栅极叠层区中的衬底的表面去掉部分衬里；
图12示出了图11的衬底，其中在衬底的表面上淀积保护层，并在第二栅极叠层区上形成光致抗蚀剂层；
图13示出了从第一栅极叠层区中的衬底的表面去掉保护层之后图12的衬底；
图14示出了预清洁工艺之后图13的衬底；
图15示出了图14的衬底，其中在衬底的选择区域中形成导电材料；
图16示出了根据第三实施例的部分半导体器件，其中在衬底上形成第一和第二栅极叠层，并在衬底的表面形成衬里；
图17示出了在离子注入期间图16的衬底；
图18示出了图17的衬底，其中从衬底的表面去掉部分衬里；
图19示出了图18的衬底，其中在衬底的表面上淀积保护层，并在第二栅极叠层区上形成光致抗蚀剂层；
图20示出了从第一栅极叠层区中的衬底的表面去掉保护层之后图19的衬底；
图21示出了预清洁工艺之后图20的衬底；
图22示出了图21的衬底，其中在衬底的选择区域中形成导电材料；
图23示出了根据第四实施例的部分半导体器件，其中在衬底上形成第一和第二栅极叠层，在衬底的表面形成衬里，并沿栅极叠层的侧壁在衬里上形成第一隔离物；
图24示出了图23的衬底，具有在离子注入期间覆盖第二栅极叠层区的光致抗蚀剂层；
图25示出了图24的衬底，其中从衬底的表面去掉部分衬里；
图26示出了图25的衬底，其中在衬底的表面上淀积保护层，并在第二栅极叠层区上形成光致抗蚀剂层；
图27示出了从第一栅极叠层区中的衬底的表面去掉保护层之后图26的衬底；
图28示出了预清洁工艺之后图27的衬底；以及
图29示出了图28的衬底，其中在衬底的选择区域中形成导电材料。
具体实施方式
虽然将展示和详细说明本发明的某些实施例，但是应当理解，只要不脱离所附权利要求书的范围，可以进行各种变化和修改。本发明的范围并不限于构成元件的数量、材料、形状、相对排列等。虽然附图试图说明本发明，但是没有必要按比例绘制。
图1示出了半导体衬底10，其中如现有技术所公知在衬底10中形成STI 12。衬底10包括硅或其它类似的材料。在STI 12的两侧将形成有源区14、16。具体地说，将在第一有源区14中形成晶体管，并将在第二有源区16中形成电阻器。每个有源区14、16具有将衬底10与栅极叠层20、22分开的栅极介质层18。可以使用常规工艺形成包括多晶硅或其它类似材料的栅极叠层20、22。
如图2所示，沿栅极叠层20、22的侧壁形成第一隔离物24。第一隔离物24包括氧化物材料或其它类似材料。可以使用氧化工艺形成第一隔离物24，其中使用化学气相淀积(CVD)、等离子体增强化学气相淀积(PECVD)或其它类似工艺在侧壁26上淀积氧化物。然后使用反应离子蚀刻(RIE)或其它类似工艺蚀刻氧化物。所形成的第一隔离物24的厚度大约为50
Figure C20041009097300101
-200
Figure C20041009097300102
。
如图3所示，在衬底10的表面上形成衬里28，保形覆盖栅极叠层20、22和第一隔离物24。衬里28包括抗蚀刻材料，例如，具有高介电常数的材料(其中“高”是指介电常数(K)至少为7，并且在7-150的范围内)。例如，衬里28包括高K材料，例如，Al2O3、HfO2、Ta2O3或其它类似材料。或者，衬里28包括除如SiC的高K材料之外的抗蚀刻材料。所形成的衬里28的厚度范围大约为25
Figure C20041009097300103
-250
Figure C20041009097300104
。可以使用CVD、原子层淀积(ALD)、等离子体辅助CVD、溅射或其它类似工艺保形淀积衬里28。
如图4所示，在衬里28上沿栅极叠层20、22的侧壁形成第二隔离物30。第二隔离物30包括绝缘材料，例如，氮化物，例如，Si3N4或其它类似的绝缘材料。可以使用CVD、PECVD或其它类似工艺淀积第二隔离物30的材料。随后，可以使用RIE或其它类似工艺去掉过多的材料，从而形成第二隔离物30。所形成的第二隔离物30的厚度大约为200
Figure C20041009097300105
-800
Figure C20041009097300106
然后将离子32，例如Ge、Xe、Si等，注入到衬底10的表面中，以破坏衬里28的暴露区34、36，或者没有被第二隔离物30覆盖的区域34、36。具体地说，通过离子注入，有意破坏在栅极叠层20、22顶部上的衬里28的暴露区34和与栅极叠层20、22相邻的衬底10上的衬里28的暴露区36。随后，使用湿蚀刻化学去除在区34和36中的衬里28的破坏部分，如图5所示。
如图6所示，在衬底10的表面上保形淀积绝缘层38。然后使用常规工艺淀积、构图并蚀刻光致抗蚀剂40，以覆盖衬底10的电阻器区16，而保留衬底10的晶体管区14不被覆盖。进行蚀刻工艺，例如，RIE或其它类似工艺，从晶体管区14中的衬底10的表面去掉绝缘层38。去掉剩下的光致抗蚀剂40，留下在衬底10的电阻器区16上的保护层38，如图7所示。
使用“预清洁”工艺清洁衬底10的表面，以准备晶体管区14中的衬底10的表面，用于形成导电材料。例如，可以进行氢氟化物(HF)化学预清洁工艺。在预清洁工艺期间，由于缺乏抗蚀刻能力，第二隔离物30也被非有意地蚀刻掉一部分。结果，减小了第二隔离物30的厚度，如图8a-c所示。具体地说，图8b示出了在进行预清洁工艺之前第二隔离物30的厚度42。此时，第二隔离物30的厚度42使其大致延伸到与栅极叠层20的底部相邻的衬里28的末端44或沿栅极叠层20底部的衬底10的一部分。在预清洁工艺之后，减小了第二隔离物30的厚度46(图8c)，从而第二隔离物30没有延伸到与栅极叠层20的底部相邻的衬里28的末端44或沿栅极叠层20底部的衬底10的一部分。在本实施例中，在电阻器栅极叠层22上的第二隔离物30不受预清洁影响，因为栅极叠层22和隔离物24、30受层38保护。
如图9所示，在晶体管栅极叠层20的顶部区34上和晶体管的源极/漏极区50中形成导电材料48，例如，硅化物或其它类似的材料。通过使用PVD、CVD、溅射或其它类似的工艺在衬底10的表面上均匀的淀积一层难熔金属，例如钴或钛，形成导电材料48。然后，例如暴露在700℃的温度下大约30秒，退火金属。在退火工艺期间，金属扩散到硅的暴露区域中，形成了硅化物。随后，化学去除未反应的钴金属。
应当注意，衬里28限定或确定了相对于晶体管栅极叠层20在哪里形成导电材料48。如果没有使用衬里28，则在源极/漏极区50中形成的导电材料48将更靠近栅极叠层20的底部，因为在导电材料48形成之前进行的预清洁工艺减小了第二隔离物30的厚度46(参考图8c)。衬里28覆盖在区域52(在预清洁工艺之前最初被第二隔离物30覆盖的区域)中的衬底10中的硅，从而防止在区域52中形成导电材料48。如果所形成的导电材料48太靠近栅极叠层20的底部，则在晶体管栅极叠层20的顶部区域34上的导电材料48与在晶体管栅极叠层20的源极/漏极区50中的导电材料48之间电短路的可能性更大。
另外，衬里28防止在预清洁工艺期间从栅极叠层20、22的侧壁上去掉第一隔离物24。因为在第一隔离物24中没有形成破口，所以栅极叠层20、22的侧壁不会受导电材料48形成的影响。如在相关技术中所说明，在晶体管栅极叠层20的侧壁26上形成的导电材料48增加了在栅极叠层20的顶部区域上的导电材料48与在源极/漏极区50中的导电材料48之间电短路的可能性。而且，在电阻器栅极叠层22的侧壁26上形成的导电材料48降低了电阻器的电阻值。
在图10-15中示出了第二实施例。在本实施例中，没有去掉在电阻器栅极叠层22的顶部区域34上的衬里28以及与电阻器栅极叠层22相邻的区域36中的衬里28。具体地说，在根据第一实施例(图1-4)在衬里28上沿晶体管和电阻器栅极叠层20、22的侧壁26形成第二隔离物30之后，在衬底10上淀积掩膜层或光致抗蚀剂层54。如图10所示，构图并蚀刻光致抗蚀剂层54，以暴露衬底10的晶体管区14。如上所述，注入的离子32将只破坏在晶体管区14中的衬里28的暴露区34、36，而不破坏在电阻器区16中的衬里28。
随后，进行湿蚀刻，以去掉在区域34和36中衬里28的破坏部分，并去掉光致抗蚀剂54，如图11所示。如在第一实施例中所述，在衬底10的表面上保形淀积保护层38(图12)。然后使用常规工艺淀积、构图并蚀刻光致抗蚀剂40，以覆盖衬底10的电阻器区16，而保留衬底10的晶体管区14不被覆盖(图12)。进行蚀刻工艺，例如，RIE或其它类似的工艺，从晶体管区14中的衬底10的表面上去掉保护层38，如图13所示。还去掉剩余的光致抗蚀剂40，留下衬底10的电阻器区16上的保护层38(图13)。
随后，进行预清洁工艺，以准备晶体管区14中的衬底10的表面，用于形成导电材料48。如上所述，在预清洁工艺期间，第二隔离物30的厚度减小(图14)。在预清洁工艺期间，沿电阻器栅极叠层22的侧壁的第二隔离物30受层38保护。另外，第一隔离物24和电阻器栅极叠层22不受预清洁的影响，因为栅极叠层22和第一隔离物24受衬里28保护。
然后，在晶体管栅极叠层20的顶部区34上和晶体管的源极/漏极区50中形成导电材料48(图15)。但是，电阻器区16没有形成导电材料48，因为覆盖电阻器区16的整个表面的衬里28确保在导电材料48预清洁工艺期间，在隔离物24、30或保护层38中没有破口。
在图16-22中示出了第三实施例。不是沿晶体管栅极叠层20和电阻器栅极叠层22的侧壁26形成第一隔离物24，而是在栅极叠层20、22上直接形成衬里28，如图16所示。随后，在衬里28上沿栅极叠层20、22的侧壁26形成隔离物30，如图17所示。
然后，将离子32注入衬底10的表面，以破坏衬里28的暴露部分，如图17所示。如在第一实施例中所述，通过离子注入有意破坏衬里28的暴露区域。然后，使用湿蚀刻化学去除衬里28的破坏部分，如图18所示。
如图19所示，在衬底10的表面上保形淀积层38。然后使用常规工艺淀积、构图并蚀刻光致抗蚀剂40，以覆盖衬底10的电阻器区16，而保留衬底10的晶体管区14不被覆盖。蚀刻工艺从晶体管区14中的衬底10的表面上去掉层38。去掉剩余的光致抗蚀剂40，留下衬底10的电阻器区16上的保护层38，如图20所示。
进行预清洁工艺，以准备晶体管区14中的衬底10的表面，用于形成导电材料48。如在第一实施例中所述，在预清洁工艺期间，蚀刻第二隔离物30，从而减小第二隔离物30的厚度，如图21所示。如在第一实施例中所述，并如图22所示，在晶体管栅极叠层20的顶部区34上和晶体管的源极/漏极区50中形成导电材料48。
第四实施例组合了第二和第三实施例的一部分，并在图16和23-29中示出。与上述第三实施例相同，在栅极叠层20、22上直接形成衬里28，而不形成第一隔离物24，如图16所示。随后，在衬里28上沿栅极叠层20、22的侧壁26形成隔离物30，如图23所示。然后，淀积、构图和蚀刻光致抗蚀剂层54，如在第二实施例中所述，从而保护衬底10的电阻器区16，并暴露衬底10的晶体管区14，如图24所示。
然后，将离子32注入衬底10的表面，以破坏衬里28的暴露区域34、36，如图24所示。如在第一实施例中所述，通过离子注入有意破坏衬里28的暴露区域34、36。但是，光致抗蚀剂层54防止电阻器区16暴露在离子32下，从而保护在电阻器区16中的衬里28不被破坏，并最终防止被去掉。在离子32注入之后，去掉光致抗蚀剂层54，然后使用湿蚀刻化学去除衬里28的破坏部分，如图25所示。
如图26所示，在衬底10的表面上保形淀积层38。然后，淀积、构图并蚀刻光致抗蚀剂40，以覆盖衬底10的电阻器区16，而保留衬底10的晶体管区14不被覆盖。蚀刻工艺从晶体管区14中的衬底10的表面上去掉层38。去掉剩余的光致抗蚀剂40，留下衬底10的电阻器区16上的保护层38，如图27所示。
进行预清洁工艺，以准备晶体管区14中的衬底10的表面，用于形成导电材料48。如在第一实施例中所述，在预清洁工艺期间，蚀刻第二隔离物30，从而减小第二隔离物30的厚度(图28)。如在第一实施例中所述，并如图29所示，在晶体管栅极叠层20的顶部区34上和晶体管的源极/漏极区50中形成导电材料48。

Claims (15)

1.一种形成半导体器件的方法，包括：
提供在衬底表面上具有栅极叠层的衬底；
覆盖栅极叠层形成衬里，其中衬里选自Al2O3、HfO2或Ta2O3；
在衬里上沿栅极叠层的侧壁形成隔离物；
从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里，并在被隔离物覆盖的衬底和栅极叠层的区域中保留衬里；
执行预清洁工艺以蚀刻未被衬里覆盖的衬底的表面；
在没有被衬里覆盖的衬底和栅极叠层的区域中形成导电材料，其中
在衬底中形成源极和漏极区，其中通过从没有被隔离物覆盖的区域去掉衬里产生的衬里的末端确定源极和漏极区导电材料的位置。
2.根据权利要求1的方法，还包括在栅极叠层上形成衬里之前：
在衬底的表面上提供第二栅极叠层。
3.根据权利要求2的方法，还包括：
在第二栅极叠层上形成衬里；以及
在衬里上沿第二栅极叠层的侧壁形成隔离物。
4.根据权利要求3的方法，还包括在从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里，并在被隔离物覆盖的衬底和栅极叠层的区域中保留衬里之前：
在衬里和第二栅极叠层的隔离物上淀积光致抗蚀剂层，以防止从第二栅极叠层上去掉衬里。
5.根据权利要求3的方法，还包括在从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里，并在被隔离物覆盖的衬底和栅极叠层的区域中保留衬里之后：
在形成导电材料之前在覆盖第二栅极叠层的衬底的表面上形成绝缘层。
6.根据权利要求2的方法，还包括在栅极叠层上形成衬里之前：
沿第一和第二栅极叠层的侧壁形成第一隔离物。
7.根据权利要求2的方法，其中栅极叠层包括晶体管栅极叠层，第二栅极叠层包括电阻器栅极叠层。
8.一种形成半导体器件的方法，包括：
提供在衬底表面上具有第一栅极叠层和第二栅极叠层的衬底；
覆盖第一和第二栅极叠层形成衬里，其中衬里选自Al2O3、HfO2或Ta2O3；
在衬里上并沿第一和第二栅极叠层的侧壁形成隔离物；
从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里；
在第二栅极叠层上形成保护层；以及
在没有被衬里覆盖的区域中形成导电材料，其中
在衬底中形成源极和漏极区，其中通过从没有被隔离物覆盖的区域去掉衬里产生的衬里的末端确定源极和漏极区导电材料的位置。
9.根据权利要求8的方法，还包括在第一和第二栅极叠层上形成衬里之前：
沿第一和第二栅极叠层的侧壁形成第一隔离物。
10.根据权利要求8的方法，还包括在从没有被隔离物覆盖的衬底和栅极叠层的区域中去掉衬里之前：
在衬里和第二栅极叠层的隔离物上淀积光致抗蚀剂层，以防止从第二栅极叠层上去掉衬里。
11.根据权利要求8的方法，还包括在形成导电材料之前：
在第二栅极叠层上形成绝缘层；以及
在衬底上进行预清洁工艺。
12.一种半导体器件，包括：
在衬底上形成的栅极叠层；
覆盖栅极叠层的侧壁和与栅极叠层相邻的部分衬底的衬里，其中衬里选自Al2O3、HfO2或Ta2O3；
在衬里上沿栅极叠层的侧壁的隔离物；以及
在栅极叠层的顶部区域中以及衬底的源极和漏极区域中的导电材料，其中源极和漏极区导电材料的位置由位于衬底上衬里的末端确定。
13.一种半导体器件，包括：
在衬底上形成的晶体管栅极叠层和电阻器栅极叠层；
沿晶体管和电阻器栅极叠层的侧壁的第一隔离物；
在晶体管和电阻器栅极叠层的第一隔离物上，并沿在晶体管和电阻器栅极叠层的底部的部分衬底的衬里，其中衬里选自Al2O3、HfO2或Ta2O3并且沿衬底向晶体管源极和漏极区延伸；
在衬里上沿至少晶体管栅极叠层侧壁的隔离物；以及
在晶体管栅极叠层的上表面中和晶体管源极和漏极区中的导电材料，其中源极和漏极区导电材料的位置由位于衬底上衬里的末端确定。
14.根据权利要求13的半导体器件，还包括：
覆盖电阻器栅极叠层和在电阻器栅极叠层的底部的部分衬底的保护层。
15.根据权利要求13的半导体器件，其中衬里覆盖整个电阻器栅极叠层和在电阻器栅极叠层的底部的部分衬底。
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US20080036017A1 (en) 2008-02-14
JP4587774B2 (ja) 2010-11-24
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US7307323B2 (en) 2007-12-11
US20050104095A1 (en) 2005-05-19
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