DE69224730T2 - Seitenwand-Abstandsstruktur für Feldeffekttransistor - Google Patents

Seitenwand-Abstandsstruktur für Feldeffekttransistor

Info

Publication number
DE69224730T2
DE69224730T2 DE69224730T DE69224730T DE69224730T2 DE 69224730 T2 DE69224730 T2 DE 69224730T2 DE 69224730 T DE69224730 T DE 69224730T DE 69224730 T DE69224730 T DE 69224730T DE 69224730 T2 DE69224730 T2 DE 69224730T2
Authority
DE
Germany
Prior art keywords
field effect
effect transistor
spacing structure
sidewall spacing
sidewall
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69224730T
Other languages
English (en)
Other versions
DE69224730D1 (de
Inventor
Fusen E Chen
Frank Randolph Bryant
Girish Anant Dixit
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Inc
Publication of DE69224730D1 publication Critical patent/DE69224730D1/de
Application granted granted Critical
Publication of DE69224730T2 publication Critical patent/DE69224730T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
DE69224730T 1991-12-31 1992-12-23 Seitenwand-Abstandsstruktur für Feldeffekttransistor Expired - Fee Related DE69224730T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US81662791A 1991-12-31 1991-12-31

Publications (2)

Publication Number Publication Date
DE69224730D1 DE69224730D1 (de) 1998-04-16
DE69224730T2 true DE69224730T2 (de) 1998-07-30

Family

ID=25221182

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69224730T Expired - Fee Related DE69224730T2 (de) 1991-12-31 1992-12-23 Seitenwand-Abstandsstruktur für Feldeffekttransistor

Country Status (4)

Country Link
US (2) US5521411A (de)
EP (1) EP0550255B1 (de)
JP (1) JPH065621A (de)
DE (1) DE69224730T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5714413A (en) * 1995-12-11 1998-02-03 Intel Corporation Method of making a transistor having a deposited dual-layer spacer structure
JP2848299B2 (ja) * 1995-12-21 1999-01-20 日本電気株式会社 半導体装置及びその製造方法
JPH09307106A (ja) * 1996-05-20 1997-11-28 Nec Corp 半導体装置の製造方法
JPH10189966A (ja) * 1996-12-26 1998-07-21 Toshiba Corp 半導体装置及びその製造方法
DE69841732D1 (de) 1997-05-13 2010-08-05 St Microelectronics Srl Verfahren zur selektiven Herstellung von Salizid über aktiven Oberflächen von MOS-Vorrichtungen
EP0878833B1 (de) * 1997-05-13 2010-06-23 STMicroelectronics Srl Verfahren zur selektiven Herstellung von Salizid über aktiven Oberflächen von MOS-Vorrichtungen
JPH1145995A (ja) * 1997-07-25 1999-02-16 Nec Kyushu Ltd 半導体装置およびその製造方法
US5925575A (en) * 1997-09-29 1999-07-20 Taiwan Semiconductor Manufacturing Company, Ltd. Dry etching endpoint procedure to protect against photolithographic misalignments
US6680233B2 (en) * 2001-10-09 2004-01-20 Advanced Micro Devices, Inc. Semiconductor device formed with disposable spacer and liner using high-K material and method of fabrication
US6548344B1 (en) 2001-11-16 2003-04-15 Infineon Technologies Ag Spacer formation process using oxide shield
US20030124783A1 (en) * 2001-12-28 2003-07-03 Rotondaro Antonio L. P. System for creating ultra-shallow dopant profiles
US7129920B2 (en) * 2002-05-17 2006-10-31 Elcos Mircrodisplay Technology, Inc. Method and apparatus for reducing the visual effects of nonuniformities in display systems
US6657267B1 (en) 2002-06-06 2003-12-02 Advanced Micro Devices, Inc. Semiconductor device and fabrication technique using a high-K liner for spacer etch stop
EP1565934A1 (de) * 2002-11-29 2005-08-24 Advanced Micro Devices, Inc. Drain- und source-ausdehnung-struktur mit dotierten spacern mit hoher dielektrizitätskonstante
US7064027B2 (en) * 2003-11-13 2006-06-20 International Business Machines Corporation Method and structure to use an etch resistant liner on transistor gate structure to achieve high device performance
US8129764B2 (en) * 2008-06-11 2012-03-06 Aptina Imaging Corporation Imager devices having differing gate stack sidewall spacers, method for forming such imager devices, and systems including such imager devices

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
US4918501A (en) * 1984-05-23 1990-04-17 Hitachi, Ltd. Semiconductor device and method of producing the same
US4727038A (en) * 1984-08-22 1988-02-23 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor device
JPS6312168A (ja) * 1986-07-03 1988-01-19 Oki Electric Ind Co Ltd Ｌｄｄｍｉｓ型電界効果トランジスタ
JPS64761A (en) * 1987-06-23 1989-01-05 Seiko Epson Corp Semiconductor device
US4908326A (en) * 1988-01-19 1990-03-13 Standard Microsystems Corporation Process for fabricating self-aligned silicide lightly doped drain MOS devices
US5139697A (en) * 1988-01-25 1992-08-18 Canon Kabushiki Kaisha Liquid crystal composition and liquid crystal device using same
JPH0728040B2 (ja) * 1988-09-20 1995-03-29 三菱電機株式会社 半導体装置およびその製造方法
JPH02273934A (ja) * 1989-04-17 1990-11-08 Oki Electric Ind Co Ltd 半導体素子およびその製造方法
US4978634A (en) * 1989-07-25 1990-12-18 Texas Instruments, Incorporated Method of making trench DRAM cell with stacked capacitor and buried lateral contact
US5200351A (en) * 1989-10-23 1993-04-06 Advanced Micro Devices, Inc. Method of fabricating field effect transistors having lightly doped drain regions
JPH0714065B2 (ja) * 1990-03-19 1995-02-15 株式会社東芝 Ｍｏｓ型半導体装置及びその製造方法
US5221632A (en) * 1990-10-31 1993-06-22 Matsushita Electric Industrial Co., Ltd. Method of proudcing a MIS transistor
US5124180A (en) * 1991-03-11 1992-06-23 Btu Engineering Corporation Method for the formation of fluorine doped metal oxide films

Also Published As

Publication number Publication date
EP0550255A3 (en) 1993-08-25
DE69224730D1 (de) 1998-04-16
US5521411A (en) 1996-05-28
US6303452B1 (en) 2001-10-16
EP0550255B1 (de) 1998-03-11
EP0550255A2 (de) 1993-07-07
JPH065621A (ja) 1994-01-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee