DE112004002156T5 - Verfahren zum Verhindern der Vergrößerung einer Kontaktlochbreite während der Kontaktherstellung - Google Patents
Verfahren zum Verhindern der Vergrößerung einer Kontaktlochbreite während der Kontaktherstellung Download PDFInfo
- Publication number
- DE112004002156T5 DE112004002156T5 DE112004002156T DE112004002156T DE112004002156T5 DE 112004002156 T5 DE112004002156 T5 DE 112004002156T5 DE 112004002156 T DE112004002156 T DE 112004002156T DE 112004002156 T DE112004002156 T DE 112004002156T DE 112004002156 T5 DE112004002156 T5 DE 112004002156T5
- Authority
- DE
- Germany
- Prior art keywords
- contact hole
- layer
- contact
- oxide layer
- natural oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
- 238000000034 method Methods 0.000 title claims abstract description 51
- 230000004888 barrier function Effects 0.000 claims abstract description 52
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 40
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 40
- 238000000151 deposition Methods 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000000992 sputter etching Methods 0.000 claims description 12
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 9
- 239000001257 hydrogen Substances 0.000 claims description 9
- 229910052739 hydrogen Inorganic materials 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 238000005137 deposition process Methods 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 2
- 238000000746 purification Methods 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 abstract description 18
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/705,631 | 2003-11-08 | ||
| US10/705,631 US7005387B2 (en) | 2003-11-08 | 2003-11-08 | Method for preventing an increase in contact hole width during contact formation |
| PCT/US2004/033417 WO2005048342A1 (en) | 2003-11-08 | 2004-10-08 | Method for preventing an increase in contact hole width during contact formation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE112004002156T5 true DE112004002156T5 (de) | 2006-09-14 |
Family
ID=34552414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE112004002156T Ceased DE112004002156T5 (de) | 2003-11-08 | 2004-10-08 | Verfahren zum Verhindern der Vergrößerung einer Kontaktlochbreite während der Kontaktherstellung |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US7005387B2 (enExample) |
| JP (1) | JP4662943B2 (enExample) |
| KR (1) | KR101180977B1 (enExample) |
| CN (1) | CN1883045A (enExample) |
| DE (1) | DE112004002156T5 (enExample) |
| GB (1) | GB2423635B (enExample) |
| TW (1) | TWI359475B (enExample) |
| WO (1) | WO2005048342A1 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080038910A1 (en) * | 2006-08-10 | 2008-02-14 | Advanced Micro Devices, Inc. | Multiple lithography for reduced negative feature corner rounding |
| US20090050471A1 (en) * | 2007-08-24 | 2009-02-26 | Spansion Llc | Process of forming an electronic device including depositing layers within openings |
| US12444651B2 (en) | 2009-08-04 | 2025-10-14 | Novellus Systems, Inc. | Tungsten feature fill with nucleation inhibition |
| JP6494940B2 (ja) * | 2013-07-25 | 2019-04-03 | ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ | 異なるサイズのフィーチャへのボイドフリータングステン充填 |
| US9972504B2 (en) | 2015-08-07 | 2018-05-15 | Lam Research Corporation | Atomic layer etching of tungsten for enhanced tungsten deposition fill |
| KR102607331B1 (ko) * | 2018-07-13 | 2023-11-29 | 에스케이하이닉스 주식회사 | 고종횡비 구조를 위한 갭필 방법 및 그를 이용한 반도체장치 제조 방법 |
| JPWO2024147230A1 (enExample) | 2023-01-05 | 2024-07-11 |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0513411A (ja) * | 1991-07-02 | 1993-01-22 | Nec Corp | 半導体装置の製造方法 |
| JPH0661181A (ja) | 1992-08-11 | 1994-03-04 | Sony Corp | バリアメタルの形成方法 |
| JP3237917B2 (ja) * | 1992-09-22 | 2001-12-10 | 沖電気工業株式会社 | 半導体素子の製造方法 |
| JPH06349824A (ja) * | 1993-06-10 | 1994-12-22 | Toshiba Corp | 半導体装置の製造方法 |
| JPH09116009A (ja) * | 1995-10-23 | 1997-05-02 | Sony Corp | 接続孔の形成方法 |
| JPH09139358A (ja) * | 1995-11-13 | 1997-05-27 | Sony Corp | 半導体装置の製造方法 |
| US5985762A (en) * | 1997-05-19 | 1999-11-16 | International Business Machines Corporation | Method of forming a self-aligned copper diffusion barrier in vias |
| TW388095B (en) * | 1997-05-20 | 2000-04-21 | United Microelectronics Corp | Method for improving planarization of dielectric layer in interconnect metal process |
| JP3201318B2 (ja) * | 1997-11-05 | 2001-08-20 | 日本電気株式会社 | 半導体装置の製造方法 |
| US5994211A (en) * | 1997-11-21 | 1999-11-30 | Lsi Logic Corporation | Method and composition for reducing gate oxide damage during RF sputter clean |
| US6303505B1 (en) * | 1998-07-09 | 2001-10-16 | Advanced Micro Devices, Inc. | Copper interconnect with improved electromigration resistance |
| US6511575B1 (en) * | 1998-11-12 | 2003-01-28 | Canon Kabushiki Kaisha | Treatment apparatus and method utilizing negative hydrogen ion |
| KR100277086B1 (ko) * | 1999-01-02 | 2000-12-15 | 윤종용 | 반도체 장치 및 그 제조 방법 |
| JP4221859B2 (ja) * | 1999-02-12 | 2009-02-12 | 株式会社デンソー | 半導体装置の製造方法 |
| US6348709B1 (en) * | 1999-03-15 | 2002-02-19 | Micron Technology, Inc. | Electrical contact for high dielectric constant capacitors and method for fabricating the same |
| JP2000323571A (ja) * | 1999-05-14 | 2000-11-24 | Sony Corp | 半導体装置の製造方法 |
| KR100316721B1 (ko) * | 2000-01-29 | 2001-12-12 | 윤종용 | 실리사이드막을 구비한 반도체소자의 제조방법 |
| KR20010077743A (ko) * | 2000-02-08 | 2001-08-20 | 박종섭 | 비트 라인 및 그 제조 방법 |
| US6498091B1 (en) * | 2000-11-01 | 2002-12-24 | Applied Materials, Inc. | Method of using a barrier sputter reactor to remove an underlying barrier layer |
| US6624066B2 (en) | 2001-02-14 | 2003-09-23 | Texas Instruments Incorporated | Reliable interconnects with low via/contact resistance |
| US20030073304A1 (en) * | 2001-10-16 | 2003-04-17 | Applied Materials, Inc. | Selective tungsten stud as copper diffusion barrier to silicon contact |
-
2003
- 2003-11-08 US US10/705,631 patent/US7005387B2/en not_active Expired - Fee Related
-
2004
- 2004-10-08 JP JP2006539499A patent/JP4662943B2/ja not_active Expired - Fee Related
- 2004-10-08 WO PCT/US2004/033417 patent/WO2005048342A1/en not_active Ceased
- 2004-10-08 CN CNA2004800337772A patent/CN1883045A/zh active Pending
- 2004-10-08 DE DE112004002156T patent/DE112004002156T5/de not_active Ceased
- 2004-10-08 KR KR1020067008659A patent/KR101180977B1/ko not_active Expired - Fee Related
- 2004-10-08 GB GB0608285A patent/GB2423635B/en not_active Expired - Fee Related
- 2004-10-18 TW TW093131505A patent/TWI359475B/zh not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR20060107763A (ko) | 2006-10-16 |
| JP4662943B2 (ja) | 2011-03-30 |
| GB2423635B (en) | 2007-05-30 |
| JP2007511087A (ja) | 2007-04-26 |
| TW200524077A (en) | 2005-07-16 |
| US20050101148A1 (en) | 2005-05-12 |
| CN1883045A (zh) | 2006-12-20 |
| TWI359475B (en) | 2012-03-01 |
| GB2423635A (en) | 2006-08-30 |
| US7005387B2 (en) | 2006-02-28 |
| GB0608285D0 (en) | 2006-06-07 |
| WO2005048342A1 (en) | 2005-05-26 |
| KR101180977B1 (ko) | 2012-09-07 |
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| Date | Code | Title | Description |
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| OP8 | Request for examination as to paragraph 44 patent law |
Ref document number: 112004002156 Country of ref document: DE Date of ref document: 20060914 Kind code of ref document: P |
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| 8127 | New person/name/address of the applicant |
Owner name: GLOBALFOUNDRIES INC., GRAND CAYMAN, KY |
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| 8128 | New person/name/address of the agent |
Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, |
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| R002 | Refusal decision in examination/registration proceedings | ||
| R003 | Refusal decision now final |