KR101180977B1 - 콘택 형성 동안에 콘택홀 폭 증가를 방지하는 방법 - Google Patents

콘택 형성 동안에 콘택홀 폭 증가를 방지하는 방법 Download PDF

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Publication number
KR101180977B1
KR101180977B1 KR1020067008659A KR20067008659A KR101180977B1 KR 101180977 B1 KR101180977 B1 KR 101180977B1 KR 1020067008659 A KR1020067008659 A KR 1020067008659A KR 20067008659 A KR20067008659 A KR 20067008659A KR 101180977 B1 KR101180977 B1 KR 101180977B1
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South Korea
Prior art keywords
contact hole
layer
contact
sputter etching
barrier layer
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Expired - Fee Related
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KR1020067008659A
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English (en)
Korean (ko)
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KR20060107763A (ko
Inventor
돈 엠. 호퍼
히로유키 키노시타
크리스티 우
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글로벌파운드리즈 인크.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76844—Bottomless liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
KR1020067008659A 2003-11-08 2004-10-08 콘택 형성 동안에 콘택홀 폭 증가를 방지하는 방법 Expired - Fee Related KR101180977B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/705,631 2003-11-08
US10/705,631 US7005387B2 (en) 2003-11-08 2003-11-08 Method for preventing an increase in contact hole width during contact formation
PCT/US2004/033417 WO2005048342A1 (en) 2003-11-08 2004-10-08 Method for preventing an increase in contact hole width during contact formation

Publications (2)

Publication Number Publication Date
KR20060107763A KR20060107763A (ko) 2006-10-16
KR101180977B1 true KR101180977B1 (ko) 2012-09-07

Family

ID=34552414

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Application Number Title Priority Date Filing Date
KR1020067008659A Expired - Fee Related KR101180977B1 (ko) 2003-11-08 2004-10-08 콘택 형성 동안에 콘택홀 폭 증가를 방지하는 방법

Country Status (8)

Country Link
US (1) US7005387B2 (enExample)
JP (1) JP4662943B2 (enExample)
KR (1) KR101180977B1 (enExample)
CN (1) CN1883045A (enExample)
DE (1) DE112004002156T5 (enExample)
GB (1) GB2423635B (enExample)
TW (1) TWI359475B (enExample)
WO (1) WO2005048342A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080038910A1 (en) * 2006-08-10 2008-02-14 Advanced Micro Devices, Inc. Multiple lithography for reduced negative feature corner rounding
US20090050471A1 (en) * 2007-08-24 2009-02-26 Spansion Llc Process of forming an electronic device including depositing layers within openings
US12444651B2 (en) 2009-08-04 2025-10-14 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
JP6494940B2 (ja) * 2013-07-25 2019-04-03 ラム リサーチ コーポレーションＬａｍ Ｒｅｓｅａｒｃｈ Ｃｏｒｐｏｒａｔｉｏｎ 異なるサイズのフィーチャへのボイドフリータングステン充填
US9972504B2 (en) 2015-08-07 2018-05-15 Lam Research Corporation Atomic layer etching of tungsten for enhanced tungsten deposition fill
KR102607331B1 (ko) * 2018-07-13 2023-11-29 에스케이하이닉스 주식회사 고종횡비 구조를 위한 갭필 방법 및 그를 이용한 반도체장치 제조 방법
DE112023002169T5 (de) 2023-01-05 2025-02-27 Fuji Electric Co., Ltd. Halbleitervorrichtung und Herstellungsverfahren dafür

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0513411A (ja) * 1991-07-02 1993-01-22 Nec Corp 半導体装置の製造方法
JPH0661181A (ja) 1992-08-11 1994-03-04 Sony Corp バリアメタルの形成方法
JP3237917B2 (ja) * 1992-09-22 2001-12-10 沖電気工業株式会社 半導体素子の製造方法
JPH06349824A (ja) * 1993-06-10 1994-12-22 Toshiba Corp 半導体装置の製造方法
JPH09116009A (ja) * 1995-10-23 1997-05-02 Sony Corp 接続孔の形成方法
JPH09139358A (ja) * 1995-11-13 1997-05-27 Sony Corp 半導体装置の製造方法
US5985762A (en) * 1997-05-19 1999-11-16 International Business Machines Corporation Method of forming a self-aligned copper diffusion barrier in vias
TW388095B (en) * 1997-05-20 2000-04-21 United Microelectronics Corp Method for improving planarization of dielectric layer in interconnect metal process
JP3201318B2 (ja) * 1997-11-05 2001-08-20 日本電気株式会社 半導体装置の製造方法
US5994211A (en) * 1997-11-21 1999-11-30 Lsi Logic Corporation Method and composition for reducing gate oxide damage during RF sputter clean
US6303505B1 (en) * 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6511575B1 (en) * 1998-11-12 2003-01-28 Canon Kabushiki Kaisha Treatment apparatus and method utilizing negative hydrogen ion
KR100277086B1 (ko) * 1999-01-02 2000-12-15 윤종용 반도체 장치 및 그 제조 방법
JP4221859B2 (ja) * 1999-02-12 2009-02-12 株式会社デンソー 半導体装置の製造方法
US6348709B1 (en) * 1999-03-15 2002-02-19 Micron Technology, Inc. Electrical contact for high dielectric constant capacitors and method for fabricating the same
JP2000323571A (ja) * 1999-05-14 2000-11-24 Sony Corp 半導体装置の製造方法
KR100316721B1 (ko) * 2000-01-29 2001-12-12 윤종용 실리사이드막을 구비한 반도체소자의 제조방법
KR20010077743A (ko) * 2000-02-08 2001-08-20 박종섭 비트 라인 및 그 제조 방법
US6498091B1 (en) * 2000-11-01 2002-12-24 Applied Materials, Inc. Method of using a barrier sputter reactor to remove an underlying barrier layer
US6624066B2 (en) 2001-02-14 2003-09-23 Texas Instruments Incorporated Reliable interconnects with low via/contact resistance
US20030073304A1 (en) * 2001-10-16 2003-04-17 Applied Materials, Inc. Selective tungsten stud as copper diffusion barrier to silicon contact

Also Published As

Publication number Publication date
TW200524077A (en) 2005-07-16
CN1883045A (zh) 2006-12-20
US20050101148A1 (en) 2005-05-12
KR20060107763A (ko) 2006-10-16
US7005387B2 (en) 2006-02-28
WO2005048342A1 (en) 2005-05-26
JP2007511087A (ja) 2007-04-26
JP4662943B2 (ja) 2011-03-30
GB2423635A (en) 2006-08-30
GB0608285D0 (en) 2006-06-07
GB2423635B (en) 2007-05-30
DE112004002156T5 (de) 2006-09-14
TWI359475B (en) 2012-03-01

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