JP4662943B2 - コンタクトの形成中、コンタクトホール幅の増大を防ぐ方法 - Google Patents
コンタクトの形成中、コンタクトホール幅の増大を防ぐ方法 Download PDFInfo
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- JP4662943B2 JP4662943B2 JP2006539499A JP2006539499A JP4662943B2 JP 4662943 B2 JP4662943 B2 JP 4662943B2 JP 2006539499 A JP2006539499 A JP 2006539499A JP 2006539499 A JP2006539499 A JP 2006539499A JP 4662943 B2 JP4662943 B2 JP 4662943B2
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- contact hole
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- barrier layer
- native oxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
Description
一例では、元からある酸化層210は、約10.0Å〜50.0Åの厚さを有してよい。バリア層202は、従来技術で周知の方法で、自然酸化物層210、及び、絶縁層204の、コンタクトホール208の側壁206及び207に堆積されてよく、また、バリア層202は、チタン/窒化チタン(“Ti/TiN”)を含むことができる。その他の実施形態では、バリア層202は、異なる金属の組合せ、あるいは適切な単一の金属、を含むことができる。本実施形態では、コンタクトホール208の上面における、上部コーナー領域222に隣接して位置する、バリア層202の各部分218の厚さが、コンタクトホール208の底部212に位置するバリア層202の各部分219よりも厚くなるように、バリア層202の堆積が最適化できる。その結果、バリア層202の各部分218は、後続のスパッタエッチングプロセス中、絶縁層204の上部コーナー領域222に、十分な保護を与える。コンタクトホール208の側壁206及び207間の距離である、コンタクトホール幅220は、本出願では、“電気接触幅”とも呼ばれる。
図2Aを参照すると、フローチャート100のステップ150の結果は、構造250によって例示される。引き続き、フローチャート100のステップ152において、図1のステップ152及び図2Bの構造252を参照すると、バリア層202の部分219及びコンタクトホール208の底部に位置する自然酸化物層210は、除去され、シリサイド層214が露出される。コンタクトホール208の底部及び自然酸化物層210に位置するバリア層202の部分219は、アルゴン(“Ar”)を含むことができる、スパッタエッチングプロセスを用いて除去できる。このスパッタエッチングプロセスによって、側壁206及び207の上部に位置する、バリア層202の各部分を除去することもできる。しかし、バリア層202(図2Aに示す)の各部分218は、絶縁層204の上部コーナー領域222を保護するのに十分な厚さを有しているので、上部コーナー領域222は、このスパッタエッチングプロセス中はエッチングされない。その結果、このスパッタエッチングプロセス中、コンタクトホール幅は増大しない。コンタクトホール208は、後続のステップで、タングステンなどの金属で充填されて、コンタクト形成が完了する。図2Bを参照すると、フローチャート100のステップ152の結果は、構造252によって例示される。
Claims (8)
- 半導体ダイに設けられたシリサイド層上にコンタクトを形成する方法であって、
コンタクトホールの側壁及び、前記コンタクトホールの底部に位置する自然酸化物層に、バリア層を堆積するステップを有し、前記側壁は、絶縁層の前記コンタクトホールにより形成されており、前記自然酸化物層は前記シリサイド層上に位置しており、
前記コンタクトホールの前記底部の前記シリサイド層上に位置する前記自然酸化物層を同時スパッタエッチング/堆積プロセスを使用して除去するステップを有する、方法。 - 前記コンタクトホールの前記底部の前記シリサイド層上に位置する前記自然酸化物層を除去する前記ステップでは、前記バリア層及び前記自然酸化物層を同時にスパッタエッチングし、かつ、前記バリア層にチタン/窒化チタンを堆積する、請求項1に記載の方法。
- 前記同時スパッタエッチング/堆積プロセスの、スパッタエッチング/堆積比は1.0より大きい、請求項1に記載の方法。
- 前記絶縁層は、前記コンタクトホールに隣接して位置する上部コーナー領域を含み、前記同時スパッタエッチング/堆積プロセスにおいては前記絶縁層の前記上部コーナー領域をエッチングしない、請求項1に記載の方法。
- 前記コンタクトホールは電気接続幅を有しており、前記電気接続幅は、前記同時スパッタエッチング/堆積プロセスでは増大しない、請求項1に記載の方法。
- 前記同時スパッタエッチング/堆積プロセスはアルゴンスパッタエッチングを含む、請求項1に記載の方法。
- 前記絶縁層は、PECVD酸化物を含む、請求項1に記載の方法。
- 半導体ダイに位置するシリサイド層上にコンタクトを形成する方法であって、
コンタクトホールの側壁、及び、前記コンタクトホールの底部に位置する自然酸化物層に、バリア層を堆積するステップを含み、前記側壁は、絶縁層の前記コンタクトホールによって形成され、
前記バリア層の一部、及び、前記コンタクトホールの底部に位置する自然酸化物層を除去し、前記シリサイド層を露出させるステップを含み、前記コンタクトホールの前記側壁に前記バリア層を堆積するステップを、前記コンタクトホールの上部におけるバリア層の厚さが、前記コンタクトホールの底部における厚さよりも大きくなるように最適化される、方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/705,631 US7005387B2 (en) | 2003-11-08 | 2003-11-08 | Method for preventing an increase in contact hole width during contact formation |
PCT/US2004/033417 WO2005048342A1 (en) | 2003-11-08 | 2004-10-08 | Method for preventing an increase in contact hole width during contact formation |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007511087A JP2007511087A (ja) | 2007-04-26 |
JP2007511087A5 JP2007511087A5 (ja) | 2007-11-29 |
JP4662943B2 true JP4662943B2 (ja) | 2011-03-30 |
Family
ID=34552414
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006539499A Expired - Fee Related JP4662943B2 (ja) | 2003-11-08 | 2004-10-08 | コンタクトの形成中、コンタクトホール幅の増大を防ぐ方法 |
Country Status (8)
Country | Link |
---|---|
US (1) | US7005387B2 (ja) |
JP (1) | JP4662943B2 (ja) |
KR (1) | KR101180977B1 (ja) |
CN (1) | CN1883045A (ja) |
DE (1) | DE112004002156T5 (ja) |
GB (1) | GB2423635B (ja) |
TW (1) | TWI359475B (ja) |
WO (1) | WO2005048342A1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080038910A1 (en) * | 2006-08-10 | 2008-02-14 | Advanced Micro Devices, Inc. | Multiple lithography for reduced negative feature corner rounding |
US20090050471A1 (en) * | 2007-08-24 | 2009-02-26 | Spansion Llc | Process of forming an electronic device including depositing layers within openings |
JP6494940B2 (ja) * | 2013-07-25 | 2019-04-03 | ラム リサーチ コーポレーションLam Research Corporation | 異なるサイズのフィーチャへのボイドフリータングステン充填 |
US9972504B2 (en) | 2015-08-07 | 2018-05-15 | Lam Research Corporation | Atomic layer etching of tungsten for enhanced tungsten deposition fill |
KR102607331B1 (ko) * | 2018-07-13 | 2023-11-29 | 에스케이하이닉스 주식회사 | 고종횡비 구조를 위한 갭필 방법 및 그를 이용한 반도체장치 제조 방법 |
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JPH0513411A (ja) * | 1991-07-02 | 1993-01-22 | Nec Corp | 半導体装置の製造方法 |
JPH06104342A (ja) * | 1992-09-22 | 1994-04-15 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
JPH06349824A (ja) * | 1993-06-10 | 1994-12-22 | Toshiba Corp | 半導体装置の製造方法 |
JPH09116009A (ja) * | 1995-10-23 | 1997-05-02 | Sony Corp | 接続孔の形成方法 |
JPH09139358A (ja) * | 1995-11-13 | 1997-05-27 | Sony Corp | 半導体装置の製造方法 |
JPH10340865A (ja) * | 1997-05-19 | 1998-12-22 | Internatl Business Mach Corp <Ibm> | ビア中に自己整合銅拡散バリヤを形成する方法 |
JPH11145078A (ja) * | 1997-11-05 | 1999-05-28 | Nec Corp | 半導体装置の製造方法 |
JP2000299310A (ja) * | 1999-02-12 | 2000-10-24 | Denso Corp | 半導体装置の製造方法 |
JP2000323571A (ja) * | 1999-05-14 | 2000-11-24 | Sony Corp | 半導体装置の製造方法 |
US6204550B1 (en) * | 1997-11-21 | 2001-03-20 | Lsi Logic Corporation | Method and composition for reducing gate oxide damage during RF sputter clean |
US6498091B1 (en) * | 2000-11-01 | 2002-12-24 | Applied Materials, Inc. | Method of using a barrier sputter reactor to remove an underlying barrier layer |
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-
2003
- 2003-11-08 US US10/705,631 patent/US7005387B2/en not_active Expired - Fee Related
-
2004
- 2004-10-08 KR KR1020067008659A patent/KR101180977B1/ko not_active IP Right Cessation
- 2004-10-08 JP JP2006539499A patent/JP4662943B2/ja not_active Expired - Fee Related
- 2004-10-08 GB GB0608285A patent/GB2423635B/en not_active Expired - Fee Related
- 2004-10-08 CN CNA2004800337772A patent/CN1883045A/zh active Pending
- 2004-10-08 DE DE112004002156T patent/DE112004002156T5/de not_active Ceased
- 2004-10-08 WO PCT/US2004/033417 patent/WO2005048342A1/en active Application Filing
- 2004-10-18 TW TW093131505A patent/TWI359475B/zh not_active IP Right Cessation
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH0513411A (ja) * | 1991-07-02 | 1993-01-22 | Nec Corp | 半導体装置の製造方法 |
JPH06104342A (ja) * | 1992-09-22 | 1994-04-15 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
JPH06349824A (ja) * | 1993-06-10 | 1994-12-22 | Toshiba Corp | 半導体装置の製造方法 |
JPH09116009A (ja) * | 1995-10-23 | 1997-05-02 | Sony Corp | 接続孔の形成方法 |
JPH09139358A (ja) * | 1995-11-13 | 1997-05-27 | Sony Corp | 半導体装置の製造方法 |
JPH10340865A (ja) * | 1997-05-19 | 1998-12-22 | Internatl Business Mach Corp <Ibm> | ビア中に自己整合銅拡散バリヤを形成する方法 |
JPH11145078A (ja) * | 1997-11-05 | 1999-05-28 | Nec Corp | 半導体装置の製造方法 |
US6204550B1 (en) * | 1997-11-21 | 2001-03-20 | Lsi Logic Corporation | Method and composition for reducing gate oxide damage during RF sputter clean |
JP2000299310A (ja) * | 1999-02-12 | 2000-10-24 | Denso Corp | 半導体装置の製造方法 |
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Also Published As
Publication number | Publication date |
---|---|
GB2423635B (en) | 2007-05-30 |
JP2007511087A (ja) | 2007-04-26 |
CN1883045A (zh) | 2006-12-20 |
GB2423635A (en) | 2006-08-30 |
DE112004002156T5 (de) | 2006-09-14 |
TW200524077A (en) | 2005-07-16 |
US20050101148A1 (en) | 2005-05-12 |
GB0608285D0 (en) | 2006-06-07 |
KR101180977B1 (ko) | 2012-09-07 |
TWI359475B (en) | 2012-03-01 |
WO2005048342A1 (en) | 2005-05-26 |
US7005387B2 (en) | 2006-02-28 |
KR20060107763A (ko) | 2006-10-16 |
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