JP2005340808A - 半導体装置のバリア構造 - Google Patents
半導体装置のバリア構造 Download PDFInfo
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- JP2005340808A JP2005340808A JP2005144753A JP2005144753A JP2005340808A JP 2005340808 A JP2005340808 A JP 2005340808A JP 2005144753 A JP2005144753 A JP 2005144753A JP 2005144753 A JP2005144753 A JP 2005144753A JP 2005340808 A JP2005340808 A JP 2005340808A
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- Prior art keywords
- barrier layer
- layer
- semiconductor device
- barrier
- conductive region
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
Abstract
【解決手段】バリア層構造を有するビア120が提供される。本具体例において、ビア120は、バリア層を形成することにより形成される。ビア120の底部に沿ったバリア層は、一部、或いは、完全に除去され、ビア120は、導電材料で充填される。もう一つの具体例において、第一バリア層130は、ビア120の側壁と底部に形成される。その後、ビア120の底部に沿った第一バリア層130は、一部、或いは、完全に除去されて、第二バリア層240が形成される。
【選択図】図1d
Description
側壁と底部を有するビアは、絶縁層上に形成され、底部は、第一導電領域の少なくとも一部分を露出している。第一バリア層は、ビアの側壁と底部に沿って形成される。ビアの底部に沿った第一バリア層の少なくとも一部は除去される。第二バリア層は、第一バリア層上に形成される。その後、ビアは、導電材料により充填される。本具体例において、側壁に沿った第一バリア層と第二バリア層の全体の厚さと、底部に沿った第一バリア層と第二バリア層の全体の厚さの比率は、0.7以上である。
110、140、242…導電層
112…エッチバッファ層
114…IMD層
120…ビア
130…第一バリア層
240…第二バリア層
Claims (12)
- 半導体装置であって、
第一導電領域と、
前記第一導電領域上の絶縁層と、
前記絶縁層内に形成され、側壁と、前記第一導電領域の少なくとも一箇所に接触する底部と、を有するビアと、
前記側壁と底部に沿って形成される一つ、或いは、それ以上のバリア層と、
からなり、
前記側壁上の一つ、或いは、それ以上の前記バリア層の全体の厚さと、前記底部上の一つ、或いは、それ以上の前記バリア層の第二の全体の厚さが、0.7以上の比率であることを特徴とする半導体装置。 - 更に、前記ビア下方の前記第一導電領域に形成されるリセスを有することを特徴とする請求項1に記載の半導体装置。
- 前記一つ、或いは、それ以上のバリア層は、タンタル、或いは、ルテニウムからなることを特徴とする請求項1に記載の半導体装置。
- 前記バリア層は、前記側壁に沿って形成される第一バリア層と、前記側壁と前記底部に沿って形成される第二バリア層と、からなることを特徴とする請求項1に記載の半導体装置。
- 前記バリア層は、第一バリア層と第二バリア層とからなり、前記第一バリア層は、前記ビアの前記底部に沿わないことを特徴とする請求項1に記載の半導体装置。
- 前記バリア層は、前記側壁と前記ボトムがほぼ等しい厚さであることを特徴とする請求項1に記載の半導体装置。
- 前記バリア層は、含ケイ素材、含窒素材、含炭素材、含水素材、金属、或いは、金属化合物層、或いは、それらの組成物であることを特徴とする請求項1に記載の半導体装置。
- 半導体装置であって、
第一導電領域と、
前記第一導電領域上の絶縁層と、
前記絶縁層内に形成され、側壁と、前記第一導電領域の少なくとも一箇所に接触する底部と、を有するビアとトレンチを有する開口と、
前記開口上に形成され、少なくともその一部が、前記トレンチの底面に沿って形成される第一バリア層と、
前記第一バリア層上に形成される第二バリア層と、
からなり、
前記側壁上の前記バリア層の全体の厚さと、前記底部の前記バリア層第二の全体の厚さが、0.7以上の比率であることを特徴とする半導体装置。 - 更に、前記ビア下方の前記第一導電領域に形成されるリセスを有することを特徴とする請求項8に記載の半導体装置。
- 一つ、或いは、それ以上の前記第一、及び、第二バリア層は、タンタル、或いは、ルテニウムからなることを特徴とする請求項8に記載の半導体装置。
- 前記第一バリア層は、前記ビアの前記底部に沿わないことを特徴とする請求項8に記載の半導体装置。
- 前記第一、及び、第二バリア層は、含ケイ素層、含炭素層、含窒素層、含水素層、金属、或いは、金属化合物層、チタン、コバルト、ニッケル、パラジウム、或いは、それらの組成物であることを特徴とする請求項8に記載の半導体装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US57441904P | 2004-05-26 | 2004-05-26 | |
US10/995,752 US20050266679A1 (en) | 2004-05-26 | 2004-11-23 | Barrier structure for semiconductor devices |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2005340808A true JP2005340808A (ja) | 2005-12-08 |
Family
ID=35581549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005144753A Withdrawn JP2005340808A (ja) | 2004-05-26 | 2005-05-17 | 半導体装置のバリア構造 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20050266679A1 (ja) |
JP (1) | JP2005340808A (ja) |
CN (1) | CN1707787A (ja) |
TW (1) | TWI257122B (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007311771A (ja) * | 2006-04-21 | 2007-11-29 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2012190854A (ja) * | 2011-03-08 | 2012-10-04 | Toshiba Corp | 半導体装置及びその配線の形成方法 |
JP2012527751A (ja) * | 2009-05-19 | 2012-11-08 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体構造体及びその形成方法 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
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US20060270234A1 (en) * | 2005-05-27 | 2006-11-30 | Varughese Mathew | Method and composition for preparing a semiconductor surface for deposition of a barrier material |
US20070126120A1 (en) * | 2005-12-06 | 2007-06-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device |
US7602068B2 (en) | 2006-01-19 | 2009-10-13 | International Machines Corporation | Dual-damascene process to fabricate thick wire structure |
US20070257366A1 (en) * | 2006-05-03 | 2007-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Barrier layer for semiconductor interconnect structure |
US7951620B2 (en) * | 2008-03-13 | 2011-05-31 | Applied Materials, Inc. | Water-barrier encapsulation method |
US9136206B2 (en) * | 2012-07-25 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Copper contact plugs with barrier layers |
US9847289B2 (en) * | 2014-05-30 | 2017-12-19 | Applied Materials, Inc. | Protective via cap for improved interconnect performance |
US10886226B2 (en) | 2018-07-31 | 2021-01-05 | Taiwan Semiconductor Manufacturing Co, Ltd. | Conductive contact having staircase barrier layers |
US11398406B2 (en) * | 2018-09-28 | 2022-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Selective deposition of metal barrier in damascene processes |
US10811382B1 (en) * | 2019-05-07 | 2020-10-20 | Nanya Technology Corporation | Method of manufacturing semiconductor device |
US11127628B1 (en) * | 2020-03-16 | 2021-09-21 | Nanya Technology Corporation | Semiconductor device with connecting structure having a step-shaped conductive feature and method for fabricating the same |
Family Cites Families (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6846739B1 (en) * | 1998-02-27 | 2005-01-25 | Micron Technology, Inc. | MOCVD process using ozone as a reactant to deposit a metal oxide barrier layer |
US5939788A (en) * | 1998-03-11 | 1999-08-17 | Micron Technology, Inc. | Copper diffusion barrier, aluminum wetting layer and improved methods for filling openings in silicon substrates with cooper |
US6191025B1 (en) * | 1999-07-08 | 2001-02-20 | Taiwan Semiconductor Manufacturing Company | Method of fabricating a damascene structure for copper medullization |
US6146991A (en) * | 1999-09-03 | 2000-11-14 | Taiwan Semiconductor Manufacturing Company | Barrier metal composite layer featuring a thin plasma vapor deposited titanium nitride capping layer |
US20030116427A1 (en) * | 2001-08-30 | 2003-06-26 | Applied Materials, Inc. | Self-ionized and inductively-coupled plasma for sputtering and resputtering |
US6727169B1 (en) * | 1999-10-15 | 2004-04-27 | Asm International, N.V. | Method of making conformal lining layers for damascene metallization |
US6395642B1 (en) * | 1999-12-28 | 2002-05-28 | Taiwan Semiconductor Manufacturing Company | Method to improve copper process integration |
US6284657B1 (en) * | 2000-02-25 | 2001-09-04 | Chartered Semiconductor Manufacturing Ltd. | Non-metallic barrier formation for copper damascene type interconnects |
US6358842B1 (en) * | 2000-08-07 | 2002-03-19 | Chartered Semiconductor Manufacturing Ltd. | Method to form damascene interconnects with sidewall passivation to protect organic dielectrics |
JP3566203B2 (ja) * | 2000-12-06 | 2004-09-15 | 株式会社東芝 | 半導体装置及びその製造方法 |
US6624066B2 (en) * | 2001-02-14 | 2003-09-23 | Texas Instruments Incorporated | Reliable interconnects with low via/contact resistance |
US6607977B1 (en) * | 2001-03-13 | 2003-08-19 | Novellus Systems, Inc. | Method of depositing a diffusion barrier for copper interconnect applications |
JP2002313757A (ja) * | 2001-04-17 | 2002-10-25 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
CN100355058C (zh) * | 2001-05-04 | 2007-12-12 | 东京毅力科创株式会社 | 具有连续沉积和蚀刻的电离pvd |
US6509267B1 (en) * | 2001-06-20 | 2003-01-21 | Advanced Micro Devices, Inc. | Method of forming low resistance barrier on low k interconnect with electrolessly plated copper seed layer |
US6576543B2 (en) * | 2001-08-20 | 2003-06-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for selectively depositing diffusion barriers |
JP3540302B2 (ja) * | 2001-10-19 | 2004-07-07 | Necエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US6797642B1 (en) * | 2002-10-08 | 2004-09-28 | Novellus Systems, Inc. | Method to improve barrier layer adhesion |
US6924221B2 (en) * | 2002-12-03 | 2005-08-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated process flow to improve copper filling in a damascene structure |
US7241696B2 (en) * | 2002-12-11 | 2007-07-10 | International Business Machines Corporation | Method for depositing a metal layer on a semiconductor interconnect structure having a capping layer |
-
2004
- 2004-11-23 US US10/995,752 patent/US20050266679A1/en not_active Abandoned
-
2005
- 2005-05-17 JP JP2005144753A patent/JP2005340808A/ja not_active Withdrawn
- 2005-05-25 TW TW094117028A patent/TWI257122B/zh active
- 2005-05-26 CN CN200510071891.0A patent/CN1707787A/zh active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007311771A (ja) * | 2006-04-21 | 2007-11-29 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2012527751A (ja) * | 2009-05-19 | 2012-11-08 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 半導体構造体及びその形成方法 |
TWI473232B (zh) * | 2009-05-19 | 2015-02-11 | Ibm | 應用於內連線之冗餘金屬阻障結構 |
JP2012190854A (ja) * | 2011-03-08 | 2012-10-04 | Toshiba Corp | 半導体装置及びその配線の形成方法 |
Also Published As
Publication number | Publication date |
---|---|
TW200539303A (en) | 2005-12-01 |
US20050266679A1 (en) | 2005-12-01 |
TWI257122B (en) | 2006-06-21 |
CN1707787A (zh) | 2005-12-14 |
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