DE69015564T2 - Vollverdiefte verbindungsstruktur mit titanium/wolfram und selektivem cvd-wolfram. - Google Patents

Vollverdiefte verbindungsstruktur mit titanium/wolfram und selektivem cvd-wolfram.

Info

Publication number
DE69015564T2
DE69015564T2 DE69015564T DE69015564T DE69015564T2 DE 69015564 T2 DE69015564 T2 DE 69015564T2 DE 69015564 T DE69015564 T DE 69015564T DE 69015564 T DE69015564 T DE 69015564T DE 69015564 T2 DE69015564 T2 DE 69015564T2
Authority
DE
Germany
Prior art keywords
tungsten
titanium
connecting structure
selective cvd
fully effected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69015564T
Other languages
English (en)
Other versions
DE69015564D1 (de
Inventor
Kuan Liao
Yu Chow
Maw-Rong Chin
Charles Rhoades
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Application granted granted Critical
Publication of DE69015564D1 publication Critical patent/DE69015564D1/de
Publication of DE69015564T2 publication Critical patent/DE69015564T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76865—Selective removal of parts of the layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69015564T 1989-04-17 1990-03-12 Vollverdiefte verbindungsstruktur mit titanium/wolfram und selektivem cvd-wolfram. Expired - Fee Related DE69015564T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/338,681 US4961822A (en) 1989-04-17 1989-04-17 Fully recessed interconnection scheme with titanium-tungsten and selective CVD tungsten
PCT/US1990/001283 WO1990013142A1 (en) 1989-04-17 1990-03-12 Fully recessed interconnection scheme with titanium-tungsten and selective cvd tungsten

Publications (2)

Publication Number Publication Date
DE69015564D1 DE69015564D1 (de) 1995-02-09
DE69015564T2 true DE69015564T2 (de) 1995-08-10

Family

ID=23325699

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69015564T Expired - Fee Related DE69015564T2 (de) 1989-04-17 1990-03-12 Vollverdiefte verbindungsstruktur mit titanium/wolfram und selektivem cvd-wolfram.

Country Status (6)

Country Link
US (1) US4961822A (de)
EP (1) EP0424485B1 (de)
JP (1) JPH0685414B2 (de)
KR (1) KR940001395B1 (de)
DE (1) DE69015564T2 (de)
WO (1) WO1990013142A1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5093710A (en) * 1989-07-07 1992-03-03 Seiko Epson Corporation Semiconductor device having a layer of titanium nitride on the side walls of contact holes and method of fabricating same
US5198298A (en) * 1989-10-24 1993-03-30 Advanced Micro Devices, Inc. Etch stop layer using polymers
JPH0682631B2 (ja) * 1990-03-16 1994-10-19 株式会社東芝 半導体装置の製造方法
US5030587A (en) * 1990-06-05 1991-07-09 Micron Technology, Inc. Method of forming substantially planar digit lines
US5382315A (en) * 1991-02-11 1995-01-17 Microelectronics And Computer Technology Corporation Method of forming etch mask using particle beam deposition
US5244538A (en) * 1991-07-26 1993-09-14 Microelectronics And Computer Technology Corporation Method of patterning metal on a substrate using direct-write deposition of a mask
JPH04320330A (ja) * 1991-04-19 1992-11-11 Sharp Corp 半導体装置のコンタクト部の形成方法
DE69220559T2 (de) * 1991-12-18 1997-12-18 Sgs Thomson Microelectronics Verfahren zur Herstellung von Kontakten in Löchern in integrierten Schaltungen
US5275973A (en) * 1993-03-01 1994-01-04 Motorola, Inc. Method for forming metallization in an integrated circuit
US6297110B1 (en) * 1994-07-29 2001-10-02 Stmicroelectronics, Inc. Method of forming a contact in an integrated circuit
US5625231A (en) * 1995-03-10 1997-04-29 Advanced Micro Devices, Inc. Low cost solution to high aspect ratio contact/via adhesion layer application for deep sub-half micrometer back-end-of line technology
TW381331B (en) * 1996-06-17 2000-02-01 Winbond Electronic Corp Manufacturing method for integrated circuit conductive plugs avoiding the generation of voids
JP3285509B2 (ja) * 1997-03-18 2002-05-27 三菱電機株式会社 半導体装置
JP2002093811A (ja) * 2000-09-11 2002-03-29 Sony Corp 電極および半導体装置の製造方法
US6383920B1 (en) 2001-01-10 2002-05-07 International Business Machines Corporation Process of enclosing via for improved reliability in dual damascene interconnects
US6770566B1 (en) 2002-03-06 2004-08-03 Cypress Semiconductor Corporation Methods of forming semiconductor structures, and articles and devices formed thereby
US6753248B1 (en) * 2003-01-27 2004-06-22 Applied Materials, Inc. Post metal barrier/adhesion film
KR101061296B1 (ko) * 2010-07-01 2011-08-31 주식회사 하이닉스반도체 반도체 소자 및 그 형성 방법
TWI403235B (zh) * 2010-07-14 2013-07-21 Taiwan Memory Company 埋藏式電路結構之製作方法
US8772155B2 (en) 2010-11-18 2014-07-08 Micron Technology, Inc. Filling cavities in semiconductor structures having adhesion promoting layer in the cavities
US8859417B2 (en) 2013-01-03 2014-10-14 Globalfoundries Inc. Gate electrode(s) and contact structure(s), and methods of fabrication thereof

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5815250A (ja) * 1981-07-21 1983-01-28 Fujitsu Ltd 半導体装置の製造方法
FR2566181B1 (fr) * 1984-06-14 1986-08-22 Commissariat Energie Atomique Procede d'autopositionnement d'une ligne d'interconnexion sur un trou de contact electrique d'un circuit integre
US4708767A (en) * 1984-10-05 1987-11-24 Signetics Corporation Method for providing a semiconductor device with planarized contacts
DE3650077T2 (de) * 1985-03-15 1995-02-23 Hewlett Packard Co Metallisches Verbindungssystem mit einer ebenen Fläche.
US4666737A (en) * 1986-02-11 1987-05-19 Harris Corporation Via metallization using metal fillets
JPH01501588A (ja) * 1986-12-19 1989-06-01 ヒユーズ・エアクラフト・カンパニー 集積回路上のコンタクトおよびバイアス用の導電プラグ
JPH0670999B2 (ja) * 1986-12-27 1994-09-07 日本電気株式会社 半導体装置の層間接続方法
JPS63257268A (ja) * 1987-04-14 1988-10-25 Nec Corp 半導体集積回路
US4808545A (en) * 1987-04-20 1989-02-28 International Business Machines Corporation High speed GaAs MESFET having refractory contacts and a self-aligned cold gate fabrication process
JPS6441240A (en) * 1987-08-07 1989-02-13 Nec Corp Semiconductor integrated circuit device
JPS6455861A (en) * 1987-08-27 1989-03-02 Mitsubishi Electric Corp Semiconductor device
JPH01225336A (ja) * 1988-03-04 1989-09-08 Mitsubishi Electric Corp 半導体装置の製造方法
JPH0234957A (ja) * 1988-07-25 1990-02-05 Matsushita Electron Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0424485B1 (de) 1994-12-28
US4961822A (en) 1990-10-09
JPH03505507A (ja) 1991-11-28
EP0424485A1 (de) 1991-05-02
WO1990013142A1 (en) 1990-11-01
KR940001395B1 (ko) 1994-02-21
JPH0685414B2 (ja) 1994-10-26
KR920700475A (ko) 1992-02-19
DE69015564D1 (de) 1995-02-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: RAYTHEON CO. (N.D.GES.D. STAATES DELAWARE), LEXING

8339 Ceased/non-payment of the annual fee