US6767768B2 - Method for forming antifuse via structure - Google Patents

Method for forming antifuse via structure Download PDF

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US6767768B2
US6767768B2 US10/328,367 US32836702A US6767768B2 US 6767768 B2 US6767768 B2 US 6767768B2 US 32836702 A US32836702 A US 32836702A US 6767768 B2 US6767768 B2 US 6767768B2
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dielectric layer
electrode
forming
layer
antifuse
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US20040012074A1 (en
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Tsong-Minn Hsieh
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United Microelectronics Corp
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United Microelectronics Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention generally relates to an antifuse via structure, and more particularly to a method of a metal via antifuse used in field programmable gate array (FPGA) for forming an antifuse via structure.
  • FPGA field programmable gate array
  • the conventional antifuse via structure comprises a substrate 100 having a first conductive wire 102 therein.
  • a first dielectric layer 104 covers on the substrate 100 and first conductive wire 102 .
  • a photoresist layer (not shown in FIG.) is formed on the first dielectric layer 104 , and performing an etching process to the first dielectric layer to expose partial conductive wire 102 to form a via open 106 in the first dielectric layer 104 .
  • a first conductive layer is deposited on the first dielectric layer 104 and to fill the via open 106 , wherein the via open 106 is on the first conductive wire 102 .
  • a polishing process such as chemical mechanical polishing (CMP) is performed to remove the excess first conductive layer to form a conductive plug 108 .
  • CMP chemical mechanical polishing
  • a buffer layer 110 is deposited before the formation of the first electrode 112 .
  • another CMP process is performed to the buffer layer 108 to remove portion of the buffer layer 110 on the surface of the conductive plug 108 to expose the portion of the conductive plug 108 .
  • a first electrode 112 of the capacitor is deposited on the buffer layer 108 by chemical vapor deposition method.
  • a second dielectric layer 114 is deposited on the first electrode 112 , wherein the second dielectric layer 114 comprises a silicon nitride layer with thickness of about 30 angstroms and a silicon oxide layer with thickness of about 130 angstroms thereon.
  • a second electrode 116 of the capacitor is formed on the second dielectric layer 114 .
  • the thickness of the second electrode 116 is thicker than the first electrode 112 as shown in FIG. 2 .
  • a capacitor structure composes of the first electrode 112 , the second dielectric layer 114 , and the second electrode 116 .
  • a third dielectric layer 118 such as silicon dioxide layer is deposited on the second electrode 116 by CVD method.
  • a photoresist layer (not shown) with an antifuse via pattern is formed on the third dielectric layer 118 by alignment process.
  • an etching process is performed to form an antifuse via open 120 in the third dielectric layer 118 .
  • a second conductive wire 122 is deposited to fill the antifuse via open 120 and on the third dielectric layer 118 .
  • the disadvantage for the conventional antifuse via structure is that the large capacitor area with lager capacitance, due to the first conductive layer is deposited to fill the tungsten keyhole such that the device processes with lower speed.
  • the capacitor area can be calculated by formula ⁇ *(D/2) 2 , wherein the ⁇ is 3.14, D is width of the second dielectric layer 114 , herein the width value of the second dielectric layer 114 is of about 0.52 um. Therefore, according to the formula, we can obtain the values of flat capacitor area is 0.212 um 2 .
  • another disadvantage is that the thin dielectric layer (second dielectric layer 114 ) is very difficult to control by plasma-enhanced chemical vapor deposition method especially for 0.15 um integrated circuit fabricating process.
  • the present invention provides a structure for improving the capacitance of the antifuse via structure.
  • the antifuse via structure comprises a substrate having a first conductive wire therein, and a first dielectric layer having a conductive plug on the substrate. Then, a buffer layer is on the first dielectric layer and partial conductive plug. Next, a first conductive layer is on the buffer layer, wherein the first conductive layer used as first electrode of the capacitor. Then, a second dielectric layer is on the first electrode. Next, as another key feature of the present invention, an antifuse via open in the second dielectric layer such that the capacitor area is smaller than the conventional flat area.
  • a third dielectric layer is on the second dielectric layer and on sidewall of antifuse via open.
  • a second electrode of capacitor is on the third dielectric layer.
  • a second conductive wire is on the top of the second electrode.
  • the present invention provides a method for forming an antifuse via structure comprising a substrate having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer with a via pattern is formed on the first dielectric layer. Next, an etching process is performed to first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to remove portion of the first conductive layer to form a conductive plug. Next, a buffer layer is deposited on the partial first dielectric layer and on the conductive plug, and another polishing process is performed to remove the partial buffer layer on the conductive plug to expose partial conductive plug.
  • a first electrode of capacitor is deposited on the buffer layer.
  • a second dielectric layer is deposited on the first electrode.
  • an intentionally misaligned process is performed to form an antifuse via open such that the breakdown will be occurred on the corner of the conductive plug.
  • the steps of forming antifuse via open include a photoresist layer is formed on the second dielectric layer by an intentionally misaligned process.
  • an etching process is performed to remove portion of the second dielectric layer to form an antifuse via open in second dielectric layer.
  • the third dielectric layer is deposited on second dielectric layer and on the sidewall of the antifuse via open.
  • a second electrode of the capacitor is deposited on the partial second dielectric layer.
  • a second conductive wire is formed on the second electrode.
  • the advantage for the process of the present invention is that the capacitor area will be shrunk such that the capacitance can be diminished as low as 1 ⁇ 3 of the original data. Furthermore, the thickness shrinking of the dielectric layer in plasma-enhanced chemical vapor deposition method can be also easily performed for 0.15 um integrated circuit fabrication process.
  • FIGS. 1 to 3 are schematic representation of structures at various stages during the formulation of a conventional antifuse via in field programmable gate array (FPGA) structure using conventional, prior art technique;
  • FPGA field programmable gate array
  • FIG. 4 is a schematic representation for forming first dielectric layer having a conductive plug on a substrate having a prior conductive wire therein in accordance with a method disclosed herein;
  • FIG. 5 is a schematic representation of the antifuse via open formed on the conductive plug by an intentionally misaligned process in accordance with a method disclosed herein;
  • FIG. 6 is a schematic representation of the antifuse via structure in a field programmable gate array in accordance with a method disclosed herein.
  • the present invention is to provide a process of metal via antifuse used in field programmable gate array (FPGA) to improve the capacitance of the semiconductor device.
  • the antifuse via structure includes a substrate having a first conductive wire and a first dielectric layer having a via open, wherein the first dielectric layer is on the substrate. Then, a first electrode of the capacitor is on the first dielectric layer and the conductive plug.
  • a second dielectric layer having an antifuse via open wherein the antifuse via open is intentionally misaligned to the conductive plug, and the portion of the second dielectric layer is on portion of the first electrode and to expose partial first electrode.
  • a third dielectric layer is on the second dielectric layer and on the sidewall of the antifuse via open.
  • a second electrode is on the third dielectric layer.
  • a second conductive wire is on the second electrode, and electrically coupled to the second electrode.
  • a first dielectric layer 14 is formed on the substrate 10 , wherein the substrate 10 having a first conductive wire 12 therein. Then, a photoresist layer (not shown) with a via pattern is formed on the first dielectric layer 14 , and then performing an etching process to form a via open 16 in the first dielectric layer 14 . Next, a first conductive layer such as tungsten (W) is deposited on the first dielectric layer 14 and to fill the via open 16 . Then, a polishing process such as chemical mechanical polishing is performed to the first conductive layer to form a conductive plug 18 . Thereafter, a buffer layer 20 is deposited on the first dielectric layer 14 , and performing another CMP process to remove the portion of buffer layer 20 to expose portion of conductive plug 18 wherein the material of buffer layer 20 comprises a silicon dioxide.
  • a first conductive layer such as tungsten (W) is deposited on the first dielectric layer 14 and to fill the via open 16 .
  • a polishing process such as chemical mechanical
  • a first electrode 22 of the capacitor is deposited on the buffer layer 20 and on the exposed surface of conductive plug 18 by chemical vapor deposition method, wherein material of the first electrode 22 can be TiN (titanium nitride.)
  • material of the first electrode 22 can be TiN (titanium nitride.)
  • an intentionally misaligned process is performed to form an antifuse via open to via open 16 , that is, to guarantee the breakdown is occurred on the corner of plug 18 . Therefore, the breakdown can be kept the same as the conventional antifuse.
  • the steps of formation of antifuse via open includes a second dielectric layer 24 is deposited on the first electrode 22 , wherein the material of second dielectric layer 24 can be silicon oxide, silicon dioxide, oxide/nitride/oxide (ONO) layer and amorphous polysilicon.
  • a photoresist layer (not shown) having an antifuse via pattern is formed on the second dielectric layer 24 by an intentionally misaligned process.
  • an etching process is performed to remove partial second dielectric layer 24 to form an antifuse via open 26 in the second dielectric layer 24 , wherein the antifuse via open 26 misaligned to the conductive plug 18 .
  • a third dielectric layer 28 is formed on the second dielectric layer and on sidewall 30 of the antifuse via open 26 by plasma-enhanced chemical vapor deposition (PECVD) method, after the antifuse via open 26 is formed in the second dielectric layer 24 such that the capacitor can be obtain capacitance as low as 1 ⁇ 3 of original data.
  • PECVD plasma-enhanced chemical vapor deposition
  • the capacitor area can be calculated by formula ⁇ *(D/2) 2 , wherein ⁇ is 3.14, D is width of the third dielectric layer 28 , herein the width of the third dielectric layer 28 of about 0.3 um. Therefore, according to the formula, we can obtain the capacitor area is of about 0.07 um 2 . To compare with the conventional flat capacitor area is of about 0.212 um 2 , the present invention only has 1 ⁇ 3 capacitor area of the original data.
  • the third dielectric layer 28 can be kept as thick as before, and the proper dielectric thickness of antifuse can be obtained by changing the antifuse via profile or aspect ratio.
  • a second electrode 32 of the capacitor is formed on the third dielectric layer 28 by sputtering method or chemical vapor deposition method.
  • the material of the second electrode 32 can be the same as the first electrode 22 .
  • a second conductive wire 34 is formed on the second electrode 32 , and electrically coupled to the second electrode 32 .
  • an intentionally misaligned process is performed to form an antifuse via open to via open 16 , that is, to guarantee the breakdown is occurred on the corner of conductive plug. Therefore, the breakdown can be kept the same as the conventional antifuse.
  • the third dielectric layer is deposited after the formation of antifuse via open in the second dielectric layer such that the capacitor area is smaller than the conventional antifuse via structure on the flat area, and the capacitance of the capacitor can be obtained as low as 1 ⁇ 3 of original data.
  • the present invention can solve the thickness shrinking in PECVD method in 0.15 um fabrication process.

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The present invention provides a method for forming an antifuse via structure. The antifuse via structures comprising a substrate that having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer is formed on the first dielectric layer. Next, an etching process is performed to etch the first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to form a conductive plug, wherein the conductive plug is on the first conductive wire. Next, a buffer layer deposited on the partial first dielectric layer and on the surface of conductive plug. Then, another polishing process is performed to the buffer layer to expose the portion of the conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer. Next, a second dielectric layer is formed on the first electrode and an intentionally misaligned process is performed to second dielectric layer to form an antifuse via open, such that the breakdown will be occurred on the corner of the first via, wherein the antifuse via open intentionally misaligned to the conductive plug. Then, a third dielectric layer and a second electrode of the capacitor are subsequently formed on the portion of the second dielectric layer and on sidewall of the antifuse via open. Finally, a second conductive wire is formed on the second electrode.

Description

“This application is a divisional of application Ser. No. 10/199,358, filed Jul. 19, 2002 now U.S. Pat. No. 6,657,277, which application(s) are incorporated herein by reference.”
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to an antifuse via structure, and more particularly to a method of a metal via antifuse used in field programmable gate array (FPGA) for forming an antifuse via structure.
2. Description of the Prior Art
Referring to FIG. 1, a structure of conventional via antifuse used in FPGAs. The conventional antifuse via structure comprises a substrate 100 having a first conductive wire 102 therein. A first dielectric layer 104 covers on the substrate 100 and first conductive wire 102. Then, a photoresist layer (not shown in FIG.) is formed on the first dielectric layer 104, and performing an etching process to the first dielectric layer to expose partial conductive wire 102 to form a via open 106 in the first dielectric layer 104. Then, a first conductive layer is deposited on the first dielectric layer 104 and to fill the via open 106, wherein the via open 106 is on the first conductive wire 102. Then, a polishing process such as chemical mechanical polishing (CMP) is performed to remove the excess first conductive layer to form a conductive plug 108.
Then, referring to FIG. 2, a buffer layer 110 is deposited before the formation of the first electrode 112. Next, another CMP process is performed to the buffer layer 108 to remove portion of the buffer layer 110 on the surface of the conductive plug 108 to expose the portion of the conductive plug 108. Then, a first electrode 112 of the capacitor is deposited on the buffer layer 108 by chemical vapor deposition method. Next, a second dielectric layer 114 is deposited on the first electrode 112, wherein the second dielectric layer 114 comprises a silicon nitride layer with thickness of about 30 angstroms and a silicon oxide layer with thickness of about 130 angstroms thereon. Then, a second electrode 116 of the capacitor is formed on the second dielectric layer 114. The thickness of the second electrode 116 is thicker than the first electrode 112 as shown in FIG. 2.
Therefore, a capacitor structure composes of the first electrode 112, the second dielectric layer 114, and the second electrode 116. Thereafter, as a key feature of the conventional metal via antifuse process, a third dielectric layer 118 such as silicon dioxide layer is deposited on the second electrode 116 by CVD method. Then, referring to FIG. 3, a photoresist layer (not shown) with an antifuse via pattern is formed on the third dielectric layer 118 by alignment process. Next, an etching process is performed to form an antifuse via open 120 in the third dielectric layer 118. Then, a second conductive wire 122 is deposited to fill the antifuse via open 120 and on the third dielectric layer 118.
The disadvantage for the conventional antifuse via structure is that the large capacitor area with lager capacitance, due to the first conductive layer is deposited to fill the tungsten keyhole such that the device processes with lower speed. The capacitor area can be calculated by formula π*(D/2)2, wherein the π is 3.14, D is width of the second dielectric layer 114, herein the width value of the second dielectric layer 114 is of about 0.52 um. Therefore, according to the formula, we can obtain the values of flat capacitor area is 0.212 um2. Furthermore, another disadvantage is that the thin dielectric layer (second dielectric layer 114) is very difficult to control by plasma-enhanced chemical vapor deposition method especially for 0.15 um integrated circuit fabricating process.
SUMMARY OF THE INVENTION
It is an object of this invention to reduce the capacitance of the antifuse via structure.
It is another object of this invention to keep the thickness of the dielectric layer at the bottom of antifuse via such that the proper dielectric thickness of antifuse can be obtained.
It is still another object of this invention to utilize an intentionally misaligned process of antifuse via to the metal plug such that the breakdown can be occurred on the corner of metal plug to keep the same as the current antifuse.
According to abovementioned objects, the present invention provides a structure for improving the capacitance of the antifuse via structure. The antifuse via structure comprises a substrate having a first conductive wire therein, and a first dielectric layer having a conductive plug on the substrate. Then, a buffer layer is on the first dielectric layer and partial conductive plug. Next, a first conductive layer is on the buffer layer, wherein the first conductive layer used as first electrode of the capacitor. Then, a second dielectric layer is on the first electrode. Next, as another key feature of the present invention, an antifuse via open in the second dielectric layer such that the capacitor area is smaller than the conventional flat area. Then, a third dielectric layer is on the second dielectric layer and on sidewall of antifuse via open. Thereafter, a second electrode of capacitor is on the third dielectric layer. Then, a second conductive wire is on the top of the second electrode. The advantage of the present invention is that the dielectric thickness of antifuse at the bottom of antifuse via is much thinner than on the flat area. Therefore, the dielectric can be kept as thick as before, and proper the dielectric thickness of antifuse can be obtained by changing the antifuse via profile or aspect ratio.
Furthermore, the present invention provides a method for forming an antifuse via structure comprising a substrate having a first conductive wire therein. Then, a first dielectric layer is formed on the substrate, and a photoresist layer with a via pattern is formed on the first dielectric layer. Next, an etching process is performed to first dielectric layer to form a via open in the first dielectric layer. Then, a first conductive layer is deposited to fill the via open and performing a polishing process to remove portion of the first conductive layer to form a conductive plug. Next, a buffer layer is deposited on the partial first dielectric layer and on the conductive plug, and another polishing process is performed to remove the partial buffer layer on the conductive plug to expose partial conductive plug. Thereafter, a first electrode of capacitor is deposited on the buffer layer. Then, a second dielectric layer is deposited on the first electrode. Next, as a key step of the present invention, an intentionally misaligned process is performed to form an antifuse via open such that the breakdown will be occurred on the corner of the conductive plug. Thus, the current antifuse can be kept as before. The steps of forming antifuse via open include a photoresist layer is formed on the second dielectric layer by an intentionally misaligned process. Then, an etching process is performed to remove portion of the second dielectric layer to form an antifuse via open in second dielectric layer. After removing the photoresist layer, the third dielectric layer is deposited on second dielectric layer and on the sidewall of the antifuse via open. Next, a second electrode of the capacitor is deposited on the partial second dielectric layer. Thereafter, a second conductive wire is formed on the second electrode.
The advantage for the process of the present invention is that the capacitor area will be shrunk such that the capacitance can be diminished as low as ⅓ of the original data. Furthermore, the thickness shrinking of the dielectric layer in plasma-enhanced chemical vapor deposition method can be also easily performed for 0.15 um integrated circuit fabrication process.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIGS. 1 to 3 are schematic representation of structures at various stages during the formulation of a conventional antifuse via in field programmable gate array (FPGA) structure using conventional, prior art technique;
FIG. 4 is a schematic representation for forming first dielectric layer having a conductive plug on a substrate having a prior conductive wire therein in accordance with a method disclosed herein;
FIG. 5 is a schematic representation of the antifuse via open formed on the conductive plug by an intentionally misaligned process in accordance with a method disclosed herein; and
FIG. 6 is a schematic representation of the antifuse via structure in a field programmable gate array in accordance with a method disclosed herein.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Some sample embodiments of the invention will now be described in greater detail. Nevertheless, it should be recognized that the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited except as specified in the accompanying claims.
According to the present invention is to provide a process of metal via antifuse used in field programmable gate array (FPGA) to improve the capacitance of the semiconductor device. The antifuse via structure includes a substrate having a first conductive wire and a first dielectric layer having a via open, wherein the first dielectric layer is on the substrate. Then, a first electrode of the capacitor is on the first dielectric layer and the conductive plug. Next, as a key feature of the present invention, a second dielectric layer having an antifuse via open, wherein the antifuse via open is intentionally misaligned to the conductive plug, and the portion of the second dielectric layer is on portion of the first electrode and to expose partial first electrode. Then, a third dielectric layer is on the second dielectric layer and on the sidewall of the antifuse via open. Next, a second electrode is on the third dielectric layer. Finally, a second conductive wire is on the second electrode, and electrically coupled to the second electrode. The advantages is that the second dielectric layer having an antifuse via open, and the antifuse via open misaligned to the conductive plug such that the capacitance area is smaller then the conventional antifuse via structure. Thus, the capacitance can be obtained as low as ⅓ of original data.
Referring to FIG. 4, a first dielectric layer 14 is formed on the substrate 10, wherein the substrate 10 having a first conductive wire 12 therein. Then, a photoresist layer (not shown) with a via pattern is formed on the first dielectric layer 14, and then performing an etching process to form a via open 16 in the first dielectric layer 14. Next, a first conductive layer such as tungsten (W) is deposited on the first dielectric layer 14 and to fill the via open 16. Then, a polishing process such as chemical mechanical polishing is performed to the first conductive layer to form a conductive plug 18. Thereafter, a buffer layer 20 is deposited on the first dielectric layer 14, and performing another CMP process to remove the portion of buffer layer 20 to expose portion of conductive plug 18 wherein the material of buffer layer 20 comprises a silicon dioxide.
Next, referring to FIG. 5, a first electrode 22 of the capacitor is deposited on the buffer layer 20 and on the exposed surface of conductive plug 18 by chemical vapor deposition method, wherein material of the first electrode 22 can be TiN (titanium nitride.) Then, as a key step of the present invention, an intentionally misaligned process is performed to form an antifuse via open to via open 16, that is, to guarantee the breakdown is occurred on the corner of plug 18. Therefore, the breakdown can be kept the same as the conventional antifuse. According to abovementioned advantages, the steps of formation of antifuse via open includes a second dielectric layer 24 is deposited on the first electrode 22, wherein the material of second dielectric layer 24 can be silicon oxide, silicon dioxide, oxide/nitride/oxide (ONO) layer and amorphous polysilicon. Then, a photoresist layer (not shown) having an antifuse via pattern is formed on the second dielectric layer 24 by an intentionally misaligned process. Next, an etching process is performed to remove partial second dielectric layer 24 to form an antifuse via open 26 in the second dielectric layer 24, wherein the antifuse via open 26 misaligned to the conductive plug 18.
Then, as another key step of the present invention, referring to FIG. 6, a third dielectric layer 28 is formed on the second dielectric layer and on sidewall 30 of the antifuse via open 26 by plasma-enhanced chemical vapor deposition (PECVD) method, after the antifuse via open 26 is formed in the second dielectric layer 24 such that the capacitor can be obtain capacitance as low as ⅓ of original data. Furthermore, another advantage is that due to the shadow effect of PECVD method, the dielectric thickness of antifuse at the bottom of antifuse via is much thinner than that on the flat area. For example, for 0.15 um integrated circuit fabrication processes, the capacitor area can be calculated by formula π*(D/2)2, wherein π is 3.14, D is width of the third dielectric layer 28, herein the width of the third dielectric layer 28 of about 0.3 um. Therefore, according to the formula, we can obtain the capacitor area is of about 0.07 um2. To compare with the conventional flat capacitor area is of about 0.212 um2, the present invention only has ⅓ capacitor area of the original data.
Therefore, the third dielectric layer 28 can be kept as thick as before, and the proper dielectric thickness of antifuse can be obtained by changing the antifuse via profile or aspect ratio. Next, a second electrode 32 of the capacitor is formed on the third dielectric layer 28 by sputtering method or chemical vapor deposition method. The material of the second electrode 32 can be the same as the first electrode 22. Thereafter, a second conductive wire 34 is formed on the second electrode 32, and electrically coupled to the second electrode 32.
According to abovementioned, we can obtain the advantages of the present invention as following:
Firstly, according to FIG. 5, an intentionally misaligned process is performed to form an antifuse via open to via open 16, that is, to guarantee the breakdown is occurred on the corner of conductive plug. Therefore, the breakdown can be kept the same as the conventional antifuse.
Secondly, according to FIG. 6, the third dielectric layer is deposited after the formation of antifuse via open in the second dielectric layer such that the capacitor area is smaller than the conventional antifuse via structure on the flat area, and the capacitance of the capacitor can be obtained as low as ⅓ of original data.
Thirdly, according to FIG. 6, due to the dielectric thickness of antifuse via at the bottom of antifuse via is much thinner than that on flat area such that the thickness of dielectric layer can be kept as thick as before, and the dielectric thickness of antifuse can be obtained by changing the antifuse via profile or aspect ratio. Therefore, the present invention can solve the thickness shrinking in PECVD method in 0.15 um fabrication process.
Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims.

Claims (16)

What is claimed is:
1. A method for forming an antifuse via structure, said method comprising:
providing a substrate having a first conductive wire therein and a first dielectric layer on said substrate;
forming a conductive plug in first dielectric layer;
forming a first electrode on said conductive plug;
forming a second dielectric layer on said first electrode;
forming an antifuse via open in said second dielectric layer, wherein said antifuse via open intentionally misaligned to said conductive plug;
forming a third dielectric layer on said second dielectric layer and on sidewall of said antifuse via open;
forming a second electrode on said third dielectric layer; and
forming a second conductive wire on said second electrode.
2. The method according to claim 6, wherein material of said conductive plug comprises tungsten.
3. The method according to claim 1, further comprising a buffer layer on said first dielectric layer.
4. The method according to claim 3, wherein material of said buffer layer comprises silicon dioxide.
5. The method according to claim 1, wherein material of said second dielectric layer comprises a silicon dioxide.
6. The method according to claim 1, wherein said forming said antifuse via open comprises an intentionally misaligned process.
7. The method according to claim 1, wherein said forming said third dielectric layer comprises a plasma-enhanced chemical vapor deposition method.
8. The method according to claim 1, wherein material of said third dielectric layer is selected from a group consisting of a silicon oxide, a silicon nitride, an oxide/nitride/oxide layer, and an amorphous polysilicon.
9. The method according to claim 1, wherein said forming said second electrode comprises a sputtering method.
10. A method for forming an antifuse via, said method comprising:
providing a substrate having a first conductive wire therein forming a first dielectric layer on said substrate;
forming a via open in said first dielectric layer;
depositing a first conductive layer to form a conductive plug;
forming a buffer layer on portion of said first dielectric layer;
depositing a first electrode on said buffer layer and on said conductive plug;
forming a second dielectric layer on said first electrode;
performing an intentionally misaligned process to form an antifuse via open in said second dielectric layer, wherein said antifuse via open intentionally misaligned to said conductive plug;
depositing a third dielectric layer on said second dielectric layer and on sidewall of said antifuse via open;
sputtering a second electrode on said third dielectric layer; and
forming a second conductive wire on said second electrode.
11. The method according to claim 10, further comprising a chemical mechanical polishing method to form said conductive plug.
12. The method according to claim 10, wherein material of said first conductive layer comprises tungsten.
13. The method according to claim 10, wherein material of said buffer layer comprises silicon dioxide.
14. The method according to claim 10, wherein material of said first electrode and said second electrode comprises titanium nitride.
15. The method according to claim 10, wherein said depositing said third dielectric layer comprises a plasma-enhanced chemical vapor deposition method.
16. The method according to claim 10, wherein material of said second dielectric layer is selected from a group consisting of a silicon oxide, a silicon nitride, an oxide/nitride/oxide layer, and an amorphous polysilicon.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9105637B2 (en) 2012-05-18 2015-08-11 International Business Machines Corporation Anti-fuse structure and fabrication
RU2579166C2 (en) * 2014-07-24 2016-04-10 Федеральное государственное учреждение "Федеральный научный центр Научно-исследовательский институт системных исследований Российской академии наук" (ФГУ ФНЦ НИИСИ РАН) Method of forming switching jumper

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040176483A1 (en) 2003-03-05 2004-09-09 Micron Technology, Inc. Cellular materials formed using surface transformation
US7132348B2 (en) * 2002-03-25 2006-11-07 Micron Technology, Inc. Low k interconnect dielectric using surface transformation
US6943065B2 (en) * 2002-03-25 2005-09-13 Micron Technology Inc. Scalable high performance antifuse structure and process
US6970373B2 (en) * 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070384A (en) 1990-04-12 1991-12-03 Actel Corporation Electrically programmable antifuse element incorporating a dielectric and amorphous silicon interlayer
US5629227A (en) * 1993-07-07 1997-05-13 Actel Corporation Process of making ESD protection devices for use with antifuses
US5726484A (en) 1996-03-06 1998-03-10 Xilinx, Inc. Multilayer amorphous silicon antifuse
US6436839B1 (en) * 1999-06-01 2002-08-20 Taiwan Semiconductor Manufacturing Company Increasing programming silicide process window by forming native oxide film on amourphous Si after metal etching

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5780323A (en) * 1990-04-12 1998-07-14 Actel Corporation Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug
US5557136A (en) * 1991-04-26 1996-09-17 Quicklogic Corporation Programmable interconnect structures and programmable integrated circuits
US5592016A (en) * 1995-04-14 1997-01-07 Actel Corporation Antifuse with improved antifuse material
US5986322A (en) * 1995-06-06 1999-11-16 Mccollum; John L. Reduced leakage antifuse structure
US6362527B1 (en) * 1996-11-21 2002-03-26 Advanced Micro Devices, Inc. Borderless vias on bottom metal
US6368900B1 (en) * 2000-02-11 2002-04-09 Chartered Semiconductor Manufacturing Ltd. Method of fabricating an antifuse element

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5070384A (en) 1990-04-12 1991-12-03 Actel Corporation Electrically programmable antifuse element incorporating a dielectric and amorphous silicon interlayer
US5629227A (en) * 1993-07-07 1997-05-13 Actel Corporation Process of making ESD protection devices for use with antifuses
US5726484A (en) 1996-03-06 1998-03-10 Xilinx, Inc. Multilayer amorphous silicon antifuse
US6436839B1 (en) * 1999-06-01 2002-08-20 Taiwan Semiconductor Manufacturing Company Increasing programming silicide process window by forming native oxide film on amourphous Si after metal etching

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9105637B2 (en) 2012-05-18 2015-08-11 International Business Machines Corporation Anti-fuse structure and fabrication
RU2579166C2 (en) * 2014-07-24 2016-04-10 Федеральное государственное учреждение "Федеральный научный центр Научно-исследовательский институт системных исследований Российской академии наук" (ФГУ ФНЦ НИИСИ РАН) Method of forming switching jumper

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CN1469463A (en) 2004-01-21
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US6657277B1 (en) 2003-12-02

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