JP4533871B2 - 不揮発性メモリにおける妨害の低減方法 - Google Patents
不揮発性メモリにおける妨害の低減方法 Download PDFInfo
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- JP4533871B2 JP4533871B2 JP2006211081A JP2006211081A JP4533871B2 JP 4533871 B2 JP4533871 B2 JP 4533871B2 JP 2006211081 A JP2006211081 A JP 2006211081A JP 2006211081 A JP2006211081 A JP 2006211081A JP 4533871 B2 JP4533871 B2 JP 4533871B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
- G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/021—Detection or location of defective auxiliary circuits, e.g. defective refresh counters in voltage or current generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/1204—Bit line control
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- Read Only Memory (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Description
図2Aと図2Bには、不揮発性メモリシステムの主要構成要素が示されている。本説明に関連する図2Aと図2B、および図3Aと図3Bの部分のみを本明細書に記載する。さらなる詳細な記載は、 Kevin M. Conley, John S. Mangan および Jeffery G. Craig による2000年2月17日出願の米国特許出願第09/505,555号(特許文献5)の「別の指定ブロック内の物理的ブロック特性の同時に起こる複数のデータセクタ・プログラミングと記憶機能とを備えたフラッシュEEPROMシステム」で知ることが可能である。上記出願は、本願明細書内に参照により取り入れられている。また、図2Aと図2B、および図3Aと図3Bは、上記特許から採られた図である。
上述したように、非選択ワードライン上で誘起される変位電流の振幅はいくつかの要因に左右される。これまで記載した本発明の局面は、上記変位電流に影響を与えるビットライン数の低減について論じるものであった。個々のワードラインの各々に起因する影響を減らすことに関連するという別の局面がある。非選択ワードラインを横切るビットライン数と、これらのビットラインにおけるレベルをセットする速度とが独立しているため、本発明の上記2つの局面は相補的なものであり、単独で独立に利用するか、一緒に利用するかのいずれかの形での利用が可能である。プログラミングの結果生じる妨害との関連で本発明の上記局面を説明するが、読出しのため、並びに、選択ワードラインのアクセスおよびビットラインの昇圧とを行う別の処理のために、上記局面を利用することも可能である。なぜなら、これらのビットラインレベルの変化によりワードラインに変位電流の誘起が再び生じる可能性があるからである。
Claims (11)
- 不揮発性メモリ素子であって、
複数のワードラインと、
複数のビットラインと、
それぞれの第1のビットラインと、それぞれの第1のワードラインと各々接続される複数の不揮発性メモリセルであって、所定のセルが接続されているそれぞれの第1のワードラインへ第1の電圧を印加し、所定のセルが接続されているそれぞれの第1のビットラインへ第2の電圧を印加することにより、前記セルのうちの所定の1つのセルに情報を記憶する不揮発性メモリセルと、
1以上の前記ビットラインと接続されたビットライン・ドライバであって、前記ドライバと接続されたビットラインへの印加電圧を前記ビットライン・ドライバが変化させる速度が調整可能であるビットライン・ドライバと、
コントローラであって、前記コントローラにより前記速度が調整可能であり、前記メモリ内の前記コントローラにより検出されたデータエラーの量に応じて、前記コントローラが前記速度を調整するコントローラと、
を備える不揮発性メモリ素子。 - 請求項1記載の不揮発性メモリ素子において、
所定のセクタがプログラムを行った回数に基づいて、前記コントローラが前記メモリの所定のセクタで前記速度を調整する不揮発性メモリ素子。 - 請求項1記載の不揮発性メモリ素子において、
前記コントローラは、前記メモリの動作条件に応じて前記速度を調整する不揮発性メモリ素子。 - 請求項3記載の不揮発性メモリ素子において、
前記動作条件に温度が含まれる不揮発性メモリ素子。 - 不揮発性メモリの動作方法であって、
複数のワードラインと、
複数のビットラインと、
それぞれの第1のビットラインと、それぞれの第1のワードラインと各々接続される複数の不揮発性メモリセルであって、所定のセルが接続されているそれぞれの第1のワードラインへ第1の電圧を印加し、所定のセルが接続されているそれぞれの第1のビットラインへ第2の電圧を印加することにより、前記セルのうちの所定の1つのセルに情報を記憶する不揮発性メモリセルと、
ある範囲の電圧を印加するために1以上の前記ビットラインと接続されたビットライン・ドライバであって、前記ドライバと接続されたビットラインへの印加電圧を前記ビットライン・ドライバが変化させる速度が調整可能であるビットライン・ドライバと、
コントローラであって、前記コントローラにより前記速度が変更されるコントローラと、を備える不揮発性メモリの動作方法において、
前記不揮発性メモリにおいて1以上のデータエラーを検出するステップと、
前記検出するステップに応じて、前記ドライバと接続されたビットラインに印加する電圧を前記ビットライン・ドライバが変化させる速度を変更するステップと、
を含む方法。 - 請求項5記載の方法において、
前記速度は、製造業者により初期値にセットされる方法。 - 請求項5記載の方法において、
前記メモリセルは複数のセクタに分割され、前記速度は前記セクタの各々において独立に変更される方法。 - 請求項7記載の方法において、
前記メモリセルが複数のセクタに分割され、前記速度は前記セクタの各々において独立に変更される方法。 - 請求項8記載の方法において、
前記速度は、前記セクタの各々の中で周期的基礎の上で変更される方法。 - 請求項9記載の方法において、
前記周期的基礎は、前記セクタが書込まれた回数により決定される方法。 - 複数のワードライン間の容量結合を用いて前記複数のワードラインを横切るように配向された複数のビットラインと、1以上の前記ビットラインと接続されたビットライン・ドライバと、コントローラとを含む不揮発性メモリシステムにおいて、少なくとも1つの選択されたビットラインに前記ビットライン・ドライバから電圧パルスを印加する方法であって、前記電圧パルスの立上がり速度をセットして、少なくとも1つのワードラインに容量結合される電流レベルの制御を行うステップを含み、前記メモリ内の前記コントローラにより検出されたデータエラーの量に応じて、前記コントローラが前記立上がり速度を調整する方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US09/703,083 US6570785B1 (en) | 2000-10-31 | 2000-10-31 | Method of reducing disturbs in non-volatile memory |
US09/759,835 US6717851B2 (en) | 2000-10-31 | 2001-01-10 | Method of reducing disturbs in non-volatile memory |
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JP2002558274A Division JP3976682B2 (ja) | 2000-10-31 | 2001-10-26 | 不揮発性メモリにおける妨害の低減方法 |
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JP2006351192A JP2006351192A (ja) | 2006-12-28 |
JP4533871B2 true JP4533871B2 (ja) | 2010-09-01 |
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JP2002558274A Expired - Lifetime JP3976682B2 (ja) | 2000-10-31 | 2001-10-26 | 不揮発性メモリにおける妨害の低減方法 |
JP2006211081A Expired - Fee Related JP4533871B2 (ja) | 2000-10-31 | 2006-08-02 | 不揮発性メモリにおける妨害の低減方法 |
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JP2002558274A Expired - Lifetime JP3976682B2 (ja) | 2000-10-31 | 2001-10-26 | 不揮発性メモリにおける妨害の低減方法 |
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US (5) | US6717851B2 (ja) |
JP (2) | JP3976682B2 (ja) |
KR (1) | KR100895216B1 (ja) |
AU (1) | AU2002251705A1 (ja) |
TW (1) | TW540054B (ja) |
WO (1) | WO2002058073A2 (ja) |
Cited By (1)
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US6717851B2 (en) | 2004-04-06 |
KR100895216B1 (ko) | 2009-05-06 |
US6888752B2 (en) | 2005-05-03 |
US20040027865A1 (en) | 2004-02-12 |
TW540054B (en) | 2003-07-01 |
WO2002058073A2 (en) | 2002-07-25 |
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US6977844B2 (en) | 2005-12-20 |
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US20020051383A1 (en) | 2002-05-02 |
JP2004524638A (ja) | 2004-08-12 |
US20050146933A1 (en) | 2005-07-07 |
JP3976682B2 (ja) | 2007-09-19 |
KR20030048103A (ko) | 2003-06-18 |
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