JP4499390B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 39
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- 239000011229 interlayer Substances 0.000 claims description 137
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 113
- 229910052802 copper Inorganic materials 0.000 claims description 109
- 239000010949 copper Substances 0.000 claims description 109
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 22
- 230000000149 penetrating effect Effects 0.000 claims description 4
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- 229910004298 SiO 2 Inorganic materials 0.000 description 1
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- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
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- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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Description
図1は、第1の実施形態における半導体装置の構造を示す断面図である。図1に示すように、本実施形態の半導体装置は、多数のトランジスタ等の半導体素子(図示せず)が形成された基板10と、基板10の上方に設けられた下層層間絶縁膜11と、下層層間絶縁膜11に形成された下層配線溝13と、下層配線溝13の壁面に沿って形成された下層バリアメタル層14と、バリアメタル層14と共に下層配線溝13を埋める銅膜15と、下層層間絶縁膜11及び銅膜15の上に設けられたシリコン窒化膜24と、シリコン窒化膜24の上に設けられた上層層間絶縁膜17と、上層層間絶縁膜17に形成された接続孔18及びその上の上層配線溝19と、接続孔18及び上層配線溝19の壁面に沿って形成された上層バリアメタル層20と、接続孔18及び上層配線溝19を埋める銅膜21とを備えている。下層配線溝13を埋める銅膜15及び下層バリアメタル層14により、下層配線16が構成されている。一方、上層層間絶縁膜17に形成された上層配線溝19は、接続孔18を包含する広い領域に形成されている。そして、上層バリアメタル層20及び銅膜21のうち、接続孔18に埋め込まれている部分が上層プラグ22aであり、上層配線溝19に埋め込まれている部分が上層配線22bである。上層プラグ22aは、シリコン窒化膜24を貫通して下層配線16の銅膜15に接触している。
図4は、第2の実施形態における半導体装置の構造を示す断面図である。図4に示すように、本実施形態の半導体装置は、多数のトランジスタ等の半導体素子(図示せず)が形成された基板10と、基板10の上方に設けられた下層層間絶縁膜11と、下層層間絶縁膜11に形成された下層配線溝13と、下層配線溝13の壁面に沿って形成された下層バリアメタル層14と、下層配線溝13を埋める銅膜15と、下層層間絶縁膜11及び銅膜15の上に設けられたシリコン窒化膜24と、シリコン窒化膜24の上に設けられた上層層間絶縁膜17と、上層層間絶縁膜17に形成された接続孔18及びその上の上層配線溝19と、接続孔18及び上層配線溝19の壁面に沿って形成された上層バリアメタル層20と、接続孔18及び上層配線溝19を埋める銅膜21とを備えている。下層配線溝13を埋める銅膜15及び下層バリアメタル層14により、下層配線16が構成されている。一方、上層層間絶縁膜17に形成された上層配線溝19は、接続孔18を包含する広い領域に形成されている。そして、上層バリアメタル層20及び銅膜21のうち、接続孔18に埋め込まれている部分が上層プラグ22aであり、上層配線溝19に埋め込まれている部分が上層配線22bである。上層プラグ22aは、シリコン窒化膜24を貫通して下層配線16の銅膜15に接触している。
図6は、第3の実施形態における半導体装置の構造を示す断面図である。図6に示すように、本実施形態の半導体装置は、多数のトランジスタ等の半導体素子(図示せず)が形成された基板10と、基板10の上方に設けられ、エッチングレートが小さい第1層11a,エッチングレートが大きい第2層11b及びエッチングレートが小さい第3層11cの3つの層からなる下層層間絶縁膜11と、下層層間絶縁膜11に形成された下層配線溝13と、下層配線溝13の壁面に沿って形成された下層バリアメタル層14と、下層配線溝13を埋める銅膜15と、下層層間絶縁膜11及び銅膜15の上に設けられたシリコン窒化膜24と、シリコン窒化膜24の上に設けられた上層層間絶縁膜17と、上層層間絶縁膜17に形成された接続孔18及びその上の上層配線溝19と、接続孔18及び上層配線溝19の壁面に沿って形成された上層バリアメタル層20と、接続孔18及び上層配線溝19を埋める銅膜21とを備えている。下層配線溝13を埋める銅膜15及び下層バリアメタル層14により、下層配線16が構成されている。一方、上層層間絶縁膜17に形成された上層配線溝19は、接続孔18を包含する広い領域に形成されている。そして、上層バリアメタル層20及び銅膜21のうち、接続孔18に埋め込まれている部分が上層プラグ22aであり、上層配線溝19に埋め込まれている部分が上層配線22bである。上層プラグ22aは、シリコン窒化膜24を貫通して下層配線16の銅膜15に接触している。
図8は、第4の実施形態における半導体装置の構造を示す断面図である。図8に示すように、本実施形態の半導体装置の基本的な構造は、第1〜第3の実施形態と同じであるが、その特徴は、第1の実施形態と第3の実施形態との特徴を併せ持つ点である。
図10は、第5の実施形態における半導体装置の構造を示す断面図である。図10に示すように、本実施形態の半導体装置は、多数のトランジスタ等の半導体素子(図示せず)が形成された基板10と、基板10の上方に設けられた下層層間絶縁膜11と、下層層間絶縁膜11に形成された下層配線溝13と、下層配線溝13の壁面に沿って形成された下層バリアメタル層14と、下層配線溝13を埋める銅膜15と、銅膜15上に形成されたバリアメタル層30と、下層層間絶縁膜11及びバリアメタル層30の上に設けられた上層層間絶縁膜17と、上層層間絶縁膜17に形成された接続孔18及びその上の上層配線溝19と、接続孔18及び上層配線溝19の壁面に沿って形成された上層バリアメタル層20と、接続孔18及び上層配線溝19を埋める銅膜21とを備えている。下層配線溝13を埋める銅膜15及び下層バリアメタル層14により、下層配線16が構成されている。一方、上層層間絶縁膜17に形成された上層配線溝19は、接続孔18を包含する広い領域に形成されている。そして、上層バリアメタル層20及び銅膜21のうち、接続孔18に埋め込まれている部分が上層プラグ22aであり、上層配線溝19に埋め込まれている部分が上層配線22bである。なお、第1〜第4の実施形態と同様に、下層層間絶縁膜11及びバリアメタル層30の上にシリコン窒化膜を形成し、シリコン窒化膜上に上層層間絶縁膜17を形成した構成であってもよい。
図12は、第6の実施形態における半導体装置の構造を示す断面図である。図12に示すように、本実施形態の半導体装置は、多数のトランジスタ等の半導体素子(図示せず)が形成された基板10と、基板10の上方に設けられた下層層間絶縁膜11と、下層層間絶縁膜11に形成された下層配線溝13と、下層配線溝13の壁面に沿って形成された下層バリアメタル層14と、下層配線溝13を埋めるSi含有銅膜35と、下層層間絶縁膜11及びSi含有銅膜35の上に設けられたシリコン窒化膜24と、シリコン窒化膜24の上に設けられた上層層間絶縁膜17と、上層層間絶縁膜17に形成された接続孔18及びその上の上層配線溝19と、接続孔18及び上層配線溝19の壁面に沿って形成された上層バリアメタル層20と、接続孔18及び上層配線溝19を埋める銅膜21とを備えている。下層配線溝13を埋めるSi含有銅膜35及び下層バリアメタル層14により、下層配線36が構成されている。一方、上層層間絶縁膜17に形成された上層配線溝19は、接続孔18を包含する広い領域に形成されている。そして、上層バリアメタル層20及び銅膜21のうち、接続孔18に埋め込まれている部分が上層プラグ22aであり、上層配線溝19に埋め込まれている部分が上層配線22bである。上層プラグ22aは、シリコン窒化膜24を貫通して下層配線16のSi含有銅膜35に接触している。
なお、上記各実施形態では、下層配線16(又は36)及び上層配線22の主要部分を銅膜によって構成したが、ポリシリコン膜、アルミニウム膜,アルミニウム合金膜、タングステン膜など、銅以外の導電性材料からなる膜を主要部とする配線を設けた場合にも、それぞれ上記各実施形態と同じ効果を発揮することができる。
11 下層層間絶縁膜
11a 下部
11b 中部
11c 上部
13 下層配線溝
13a 凹部
13b 凹凸部
13c 凹部
14 下層バリアメタル層
15 銅膜
16 下層配線
16a 凸部
16b 凹凸部
16c 凸部
17 上層層間絶縁膜
18 接続孔
19 上層配線溝
20 上層バリアメタル層
21 銅膜
22a 上層プラグ
22b 上層配線
24 シリコン窒化膜
30 バリアメタル層
35 Si含有銅膜
36 下層配線
Re レジスト膜
Claims (10)
- 半導体素子が設けられた基板と、
上記基板の上方に設けられた下層層間絶縁膜と、
上記下層層間絶縁膜に設けられた下層配線溝と、
上記下層配線溝に設けられた下層配線と、
上記下層層間絶縁膜及び上記下層配線の上方に設けられた上層層間絶縁膜と、
上記上層層間絶縁膜を貫通して上記下層配線の一部に接触する上層プラグとを備え、
上記下層層間絶縁膜における上記下層配線溝の底面には、複数の凹部が設けられることにより格子状の凸部が形成されており、
上記下層配線の底面には、上記複数の凹部に倣った形状を有する凸部が設けられている半導体装置。 - 請求項1記載の半導体装置において、
上記下層配線は、上記下層配線溝の壁面に沿って形成されたTaN膜からなるバリアメタル層と、上記バリアメタル層の上に形成された銅膜とからなる,半導体装置。 - 請求項2記載の半導体装置において、
上記下層配線の上記銅膜を覆うように、上記銅膜と上記上層層間絶縁膜との間に形成されたシリコン窒化膜を備えている,半導体装置。 - 請求項2記載の半導体装置において、
上記下層配線の上記銅膜を覆うように、上記銅膜と上記上層層間絶縁膜との間に形成されたSiON膜、SiOF膜、SiC膜又はSiCF膜を備えている,半導体装置。 - 半導体素子が設けられた基板と、
上記基板の上方に設けられた下層層間絶縁膜と、
上記下層層間絶縁膜に設けられた下層配線溝と、
上記下層配線溝内に設けられた下層配線と、
上記下層配線の上面を覆うストレス緩和用導体膜と、
上記ストレス緩和用導体膜の上方に設けられた上層層間絶縁膜と、
上記上層層間絶縁膜を貫通して上記ストレス緩和用導体膜の一部に接触する上層プラグとを備え、
上記ストレス緩和用導体膜は、上記下層配線における銅膜の上に上記下層層間絶縁膜の上面と平坦になるように形成されている半導体装置。 - 請求項5記載の半導体装置において、
上記下層配線は、上記下層配線溝の壁面に沿って形成されたTaN膜からなるバリアメタル層と、上記バリアメタル層上に形成された上記銅膜とからなる,半導体装置。 - 請求項5又は6記載の半導体装置において、
上記ストレス緩和用導体膜は、TaN膜である,半導体装置。 - 半導体素子が設けられた基板上に下層層間絶縁膜を形成する工程(a)と、
上記下層層間絶縁膜に下層配線溝を形成する工程(b)と、
上記下層配線溝の底面上に複数の開口部を有するエッチングマスクを用いて上記下層層間絶縁膜をエッチングして、上記下層層間絶縁膜における上記下層配線溝の底面に複数の凹部を設けることにより、格子状の凸部を形成する工程(c)と、
上記下層配線溝を導体材料によって埋めて、上記凹部に倣った形状の凸部を底面に有する下層配線を形成する工程(d)と、
上記下層層間絶縁膜及び上記下層配線の上方に上層層間絶縁膜を形成する工程(e)と、
上記上層層間絶縁膜を貫通して上記下層配線の一部に接触する上層プラグを形成する工程(f)と
を含む半導体装置の製造方法。 - 半導体素子が設けられた基板上に下層層間絶縁膜を形成する工程(a)と、
上記下層層間絶縁膜に、下層配線溝を形成する工程(b)と、
上記下層配線溝を導体材料によって埋めて下層配線を形成する工程(c)と、
上記下層配線における銅膜をエッチングして、上記銅膜を掘り下げる工程(d)と、
上記工程(d)よりも後に、上記下層配線及び上記下層層間絶縁膜の上に、ストレス緩和用導体膜を形成する工程(e)と、
CMP法により、上記下層層間絶縁膜の上面が露出するまで上記ストレス緩和用導体膜を除去することにより、エッチングにより掘り下げられた上記銅膜の上に上記ストレス緩和用導体膜を形成する工程(f)と、
上記工程(f)よりも後に、上記下層層間絶縁膜及び上記ストレス緩和用導体膜の上方に上層層間絶縁膜を形成する工程(g)と、
上記上層層間絶縁膜を貫通して上記ストレス緩和用導体膜の一部に接触する上層プラグを形成する工程(h)と
を含む半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
上記ストレス緩和用導体膜は、TaN膜である,半導体装置の製造方法。
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CNB2004100768474A CN1314102C (zh) | 2003-09-09 | 2004-09-08 | 半导体装置及其制造方法 |
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