JP4469319B2 - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

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Publication number
JP4469319B2
JP4469319B2 JP2005282199A JP2005282199A JP4469319B2 JP 4469319 B2 JP4469319 B2 JP 4469319B2 JP 2005282199 A JP2005282199 A JP 2005282199A JP 2005282199 A JP2005282199 A JP 2005282199A JP 4469319 B2 JP4469319 B2 JP 4469319B2
Authority
JP
Japan
Prior art keywords
memory cell
voltage
bit line
word line
cell array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005282199A
Other languages
English (en)
Japanese (ja)
Other versions
JP2007026627A (ja
Inventor
雅之 田尻
篤志 島岡
剛至 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2005282199A priority Critical patent/JP4469319B2/ja
Priority to US11/921,755 priority patent/US7668001B2/en
Priority to PCT/JP2006/309086 priority patent/WO2006134732A1/ja
Priority to KR1020087000541A priority patent/KR100909199B1/ko
Priority to CN2006800215717A priority patent/CN101199023B/zh
Priority to TW095117770A priority patent/TW200703622A/zh
Publication of JP2007026627A publication Critical patent/JP2007026627A/ja
Application granted granted Critical
Publication of JP4469319B2 publication Critical patent/JP4469319B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G11C2013/009—Write using potential difference applied between cell electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Landscapes

  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
JP2005282199A 2005-06-17 2005-09-28 半導体記憶装置 Expired - Fee Related JP4469319B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2005282199A JP4469319B2 (ja) 2005-06-17 2005-09-28 半導体記憶装置
US11/921,755 US7668001B2 (en) 2005-06-17 2006-01-05 Semiconductor memory device
PCT/JP2006/309086 WO2006134732A1 (ja) 2005-06-17 2006-05-01 半導体記憶装置
KR1020087000541A KR100909199B1 (ko) 2005-06-17 2006-05-01 반도체 기억 장치
CN2006800215717A CN101199023B (zh) 2005-06-17 2006-05-01 半导体存储装置
TW095117770A TW200703622A (en) 2005-06-17 2006-05-19 Semiconductor storage apparatus

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005178395 2005-06-17
JP2005282199A JP4469319B2 (ja) 2005-06-17 2005-09-28 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2007026627A JP2007026627A (ja) 2007-02-01
JP4469319B2 true JP4469319B2 (ja) 2010-05-26

Family

ID=37532099

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005282199A Expired - Fee Related JP4469319B2 (ja) 2005-06-17 2005-09-28 半導体記憶装置

Country Status (6)

Country Link
US (1) US7668001B2 (https=)
JP (1) JP4469319B2 (https=)
KR (1) KR100909199B1 (https=)
CN (1) CN101199023B (https=)
TW (1) TW200703622A (https=)
WO (1) WO2006134732A1 (https=)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI331343B (en) * 2007-03-28 2010-10-01 Nanya Technology Corp A compensation circuit and a memory with the compensation circuit
JP4252624B2 (ja) * 2007-06-01 2009-04-08 パナソニック株式会社 抵抗変化型記憶装置
JP5072564B2 (ja) 2007-12-10 2012-11-14 株式会社東芝 半導体記憶装置及びメモリセル電圧印加方法
JP5063337B2 (ja) * 2007-12-27 2012-10-31 株式会社日立製作所 半導体装置
TWI413121B (zh) 2008-02-29 2013-10-21 Toshiba Kk Semiconductor memory device
US8363365B2 (en) * 2008-06-17 2013-01-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2010009669A (ja) 2008-06-26 2010-01-14 Toshiba Corp 半導体記憶装置
KR20100011292A (ko) 2008-07-24 2010-02-03 삼성전자주식회사 수직 스트링 상변화 메모리 소자
JP5106297B2 (ja) * 2008-07-30 2012-12-26 株式会社東芝 半導体記憶装置
KR20100095079A (ko) * 2009-02-20 2010-08-30 삼성전자주식회사 가변저항 메모리 셀 어레이를 갖는 저항성 메모리 장치, 이를 포함하는 메모리 시스템, 및 그것의 데이터 입출력 방법
JP5175769B2 (ja) * 2009-02-25 2013-04-03 株式会社東芝 半導体記憶装置
WO2010109803A1 (ja) * 2009-03-25 2010-09-30 パナソニック株式会社 抵抗変化型不揮発性記憶装置
KR20100123149A (ko) 2009-05-14 2010-11-24 삼성전자주식회사 저항체를 이용한 반도체 메모리 장치
JP2011040112A (ja) 2009-08-06 2011-02-24 Toshiba Corp 不揮発性半導体記憶装置
JP4940287B2 (ja) * 2009-08-06 2012-05-30 株式会社東芝 不揮発性半導体記憶装置
JP5214560B2 (ja) * 2009-08-19 2013-06-19 株式会社東芝 不揮発性半導体記憶装置
US8289749B2 (en) * 2009-10-08 2012-10-16 Sandisk 3D Llc Soft forming reversible resistivity-switching element for bipolar switching
KR101652333B1 (ko) 2010-02-10 2016-08-30 삼성전자주식회사 가변 저항 메모리 장치 및 그것의 프로그램 방법
US8848430B2 (en) * 2010-02-23 2014-09-30 Sandisk 3D Llc Step soft program for reversible resistivity-switching elements
JP2012069216A (ja) * 2010-09-24 2012-04-05 Toshiba Corp 不揮発性半導体記憶装置
US8441853B2 (en) 2010-09-30 2013-05-14 Sandisk Technologies Inc. Sensing for NAND memory based on word line position
US8971090B2 (en) 2012-08-31 2015-03-03 Kabushiki Kaisha Toshiba Semiconductor memory device
US9299410B2 (en) * 2013-09-04 2016-03-29 Shintaro SAKAI Reading magnetic memory based on regions within a cell array
US9082502B2 (en) 2013-10-10 2015-07-14 Sandisk Technologies Inc. Bit line and compare voltage modulation for sensing nonvolatile storage elements
KR102379705B1 (ko) 2015-08-20 2022-03-28 삼성전자주식회사 그라운드 스위치를 갖는 메모리 장치
CN111951874B (zh) * 2019-05-14 2022-10-18 兆易创新科技集团股份有限公司 一种校验的方法和装置
KR102685561B1 (ko) * 2020-02-28 2024-07-17 고쿠리츠 다이가꾸 호우진 시즈오까 다이가꾸 랜덤액세스형 메모리 회로 및 메모리 시스템
JP7150787B2 (ja) 2020-07-31 2022-10-11 ウィンボンド エレクトロニクス コーポレーション 抵抗変化型クロスバーアレイ装置
US11205480B1 (en) * 2020-09-11 2021-12-21 Micron Technology, Inc. Ramp-based biasing in a memory device
US11705177B2 (en) * 2021-03-12 2023-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor memory devices and methods of manufacturing thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6204139B1 (en) * 1998-08-25 2001-03-20 University Of Houston Method for switching the properties of perovskite materials used in thin film resistors
US6473332B1 (en) * 2001-04-04 2002-10-29 The University Of Houston System Electrically variable multi-state resistance computing
US6824814B2 (en) 2002-05-21 2004-11-30 Sharp Laboratories Of America, Inc. Preparation of LCPMO thin films which have reversible resistance change properties
JP2005032401A (ja) 2003-06-17 2005-02-03 Sharp Corp 不揮発性半導体記憶装置及びその書き込み方法と消去方法
DE102005004338B4 (de) * 2004-02-04 2009-04-09 Samsung Electronics Co., Ltd., Suwon Phasenänderungs-Speicherbauelement und zugehöriges Programmierverfahren
KR100520228B1 (ko) 2004-02-04 2005-10-11 삼성전자주식회사 상변화 메모리 장치 및 그에 따른 데이터 라이팅 방법
JP4365737B2 (ja) * 2004-06-30 2009-11-18 シャープ株式会社 可変抵抗素子の駆動方法及び記憶装置
JP4148210B2 (ja) 2004-09-30 2008-09-10 ソニー株式会社 記憶装置及び半導体装置
KR100670701B1 (ko) * 2004-10-30 2007-01-17 주식회사 하이닉스반도체 저 전압용 반도체 메모리 장치
KR100659502B1 (ko) * 2005-02-04 2006-12-20 삼성전자주식회사 플래쉬 셀로 구현한 퓨즈 어레이 회로
KR101509836B1 (ko) * 2007-11-13 2015-04-06 애플 인크. 멀티 유닛 메모리 디바이스에서의 메모리 유닛의 최적화된 선택

Also Published As

Publication number Publication date
CN101199023A (zh) 2008-06-11
TWI297946B (https=) 2008-06-11
US7668001B2 (en) 2010-02-23
JP2007026627A (ja) 2007-02-01
TW200703622A (en) 2007-01-16
KR100909199B1 (ko) 2009-07-23
KR20080022184A (ko) 2008-03-10
CN101199023B (zh) 2013-04-17
US20090135641A1 (en) 2009-05-28
WO2006134732A1 (ja) 2006-12-21

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