JP4212293B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4212293B2
JP4212293B2 JP2002111571A JP2002111571A JP4212293B2 JP 4212293 B2 JP4212293 B2 JP 4212293B2 JP 2002111571 A JP2002111571 A JP 2002111571A JP 2002111571 A JP2002111571 A JP 2002111571A JP 4212293 B2 JP4212293 B2 JP 4212293B2
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Japan
Prior art keywords
film
semiconductor device
manufacturing
semiconductor wafer
support
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Expired - Fee Related
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JP2002111571A
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Japanese (ja)
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JP2003309221A (ja
JP2003309221A5 (enExample
Inventor
崇 野間
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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Priority to JP2002111571A priority Critical patent/JP4212293B2/ja
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Publication of JP2003309221A5 publication Critical patent/JP2003309221A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05025—Disposition the internal layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/11001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2002111571A 2002-04-15 2002-04-15 半導体装置の製造方法 Expired - Fee Related JP4212293B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002111571A JP4212293B2 (ja) 2002-04-15 2002-04-15 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002111571A JP4212293B2 (ja) 2002-04-15 2002-04-15 半導体装置の製造方法

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2006088904A Division JP4425235B2 (ja) 2006-03-28 2006-03-28 半導体装置及びその製造方法
JP2006292233A Division JP4443549B2 (ja) 2006-10-27 2006-10-27 半導体装置の製造方法

Publications (3)

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JP2003309221A JP2003309221A (ja) 2003-10-31
JP2003309221A5 JP2003309221A5 (enExample) 2005-09-22
JP4212293B2 true JP4212293B2 (ja) 2009-01-21

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Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4340517B2 (ja) 2003-10-30 2009-10-07 Ｏｋｉセミコンダクタ株式会社 半導体装置及びその製造方法
JP2005235860A (ja) * 2004-02-17 2005-09-02 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4850392B2 (ja) 2004-02-17 2012-01-11 三洋電機株式会社 半導体装置の製造方法
TWI249767B (en) * 2004-02-17 2006-02-21 Sanyo Electric Co Method for making a semiconductor device
JP2005303258A (ja) * 2004-03-16 2005-10-27 Fujikura Ltd デバイス及びその製造方法
CN101373747B (zh) * 2004-03-16 2011-06-29 株式会社藤仓 具有通孔互连的装置及其制造方法
JP2005277173A (ja) * 2004-03-25 2005-10-06 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4544902B2 (ja) * 2004-04-26 2010-09-15 三洋電機株式会社 半導体装置及びその製造方法
JP4746847B2 (ja) * 2004-04-27 2011-08-10 三洋電機株式会社 半導体装置の製造方法
TWI272683B (en) 2004-05-24 2007-02-01 Sanyo Electric Co Semiconductor device and manufacturing method thereof
JP4518995B2 (ja) * 2004-05-24 2010-08-04 三洋電機株式会社 半導体装置及びその製造方法
JP4373866B2 (ja) 2004-07-16 2009-11-25 三洋電機株式会社 半導体装置の製造方法
JP4376715B2 (ja) * 2004-07-16 2009-12-02 三洋電機株式会社 半導体装置の製造方法
JP4524156B2 (ja) * 2004-08-30 2010-08-11 新光電気工業株式会社 半導体装置及びその製造方法
JP4139803B2 (ja) 2004-09-28 2008-08-27 シャープ株式会社 半導体装置の製造方法
JP4966487B2 (ja) 2004-09-29 2012-07-04 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
TWI267183B (en) 2004-09-29 2006-11-21 Sanyo Electric Co Semiconductor device and manufacturing method of the same
JP4936695B2 (ja) * 2004-09-29 2012-05-23 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
JP4246132B2 (ja) 2004-10-04 2009-04-02 シャープ株式会社 半導体装置およびその製造方法
JP4845368B2 (ja) * 2004-10-28 2011-12-28 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
JP5036127B2 (ja) * 2004-10-26 2012-09-26 オンセミコンダクター・トレーディング・リミテッド 半導体装置の製造方法
TWI303864B (en) 2004-10-26 2008-12-01 Sanyo Electric Co Semiconductor device and method for making the same
JP4443379B2 (ja) 2004-10-26 2010-03-31 三洋電機株式会社 半導体装置の製造方法
JP4873517B2 (ja) * 2004-10-28 2012-02-08 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
WO2006059589A1 (ja) 2004-11-30 2006-06-08 Kyushu Institute Of Technology パッケージングされた積層型半導体装置及びその製造方法
US7485967B2 (en) 2005-03-10 2009-02-03 Sanyo Electric Co., Ltd. Semiconductor device with via hole for electric connection
JP2007036060A (ja) * 2005-07-28 2007-02-08 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP4745007B2 (ja) * 2005-09-29 2011-08-10 三洋電機株式会社 半導体装置及びその製造方法
JP2007180395A (ja) * 2005-12-28 2007-07-12 Sanyo Electric Co Ltd 半導体装置の製造方法
JP4619308B2 (ja) * 2006-03-07 2011-01-26 三洋電機株式会社 半導体装置の製造方法及び支持テープ
JP5242063B2 (ja) * 2006-03-22 2013-07-24 株式会社フジクラ 配線基板の製造方法
JP2007305960A (ja) * 2006-04-14 2007-11-22 Sharp Corp 半導体装置およびその製造方法
JP2008041987A (ja) * 2006-08-08 2008-02-21 Tokyo Ohka Kogyo Co Ltd サポートプレートとウェハとの剥離方法及び装置
JP2009272490A (ja) * 2008-05-08 2009-11-19 Oki Semiconductor Co Ltd 半導体装置および半導体装置の製造方法
CN102598225B (zh) 2009-10-16 2014-12-03 英派尔科技开发有限公司 向半导体晶片应用膜的设备和方法、处理半导体晶片的方法
JP5258735B2 (ja) * 2009-11-13 2013-08-07 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー 半導体装置
JP5412316B2 (ja) 2010-02-23 2014-02-12 パナソニック株式会社 半導体装置、積層型半導体装置及び半導体装置の製造方法
JP2010251791A (ja) * 2010-06-24 2010-11-04 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP5870493B2 (ja) * 2011-02-24 2016-03-01 セイコーエプソン株式会社 半導体装置、センサーおよび電子デバイス
EP2731129A1 (en) * 2012-11-07 2014-05-14 ams AG Molded semiconductor sensor device and method of producing the same at a wafer-level
JP2015115446A (ja) 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
JP2019145737A (ja) * 2018-02-23 2019-08-29 ソニーセミコンダクタソリューションズ株式会社 半導体装置および半導体装置の製造方法
CN115206788B (zh) * 2022-07-12 2025-09-09 深圳市尚鼎芯科技股份有限公司 一种增加晶圆强度的晶圆制备方法

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