JP3197788B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法Info
- Publication number
- JP3197788B2 JP3197788B2 JP12023695A JP12023695A JP3197788B2 JP 3197788 B2 JP3197788 B2 JP 3197788B2 JP 12023695 A JP12023695 A JP 12023695A JP 12023695 A JP12023695 A JP 12023695A JP 3197788 B2 JP3197788 B2 JP 3197788B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor
- chip
- semiconductor substrate
- tape
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- Condensed Matter Physics & Semiconductors (AREA)
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Description
関し、特に極めて薄い半導体装置を安定かつ低コストで
形成するのに好適な半導体装置の製造方法に関する。
たとえば「LSIハンドブック」(社団法人電子通信学
会編株式会社オーム社、昭和59年11月30日発行、
第406頁〜416頁)などに記載されており、これら
従来の半導体装置の組立て技術では、直接ハンドリング
を行っても、割れないほぼ200μm以上の厚さを有す
る半導体チップが扱われていた。
ウエハを薄くする手段としては、研磨法が広く用いられ
ている。しかし、研磨法によって半導体ウエハを均一
に、たとえば5%以内の加工精度で加工するためには、
ウエハと研磨装置の並行出しを、高精度かつ高い再現性
で行わなう必要があり、このような極めて高い並行出し
を行うためには、極めて高価な装置が必要であり、実用
は困難であった。また、半導体ウエハの厚さをモニタし
ながら、研磨を行う方法も行われているが、広い範囲の
厚さ領域でこの方法を行うと、所要時間が著しく長くな
って生産性が低下してしまう。
1μmの程度と極めて薄くなるまで研磨を行うと、半導
体ウエハ表面のデバイスが、研磨によって生ずるストレ
スのために破壊されてしまうという問題もあった。さら
に、このように薄くされた半導体チップを、上記従来技
術によって直接ハンドリングを行うと、半導体チップ自
体が破壊されてしまうという問題があり、高い歩留と低
いコストで、半導体装置を形成するのは困難であった。
題を解決し、半導体チップの厚さを0.1から110μ
m程度まで薄くすることができ、かつ、このような極め
て薄いチップを、割れの発生なしにハンドリングするこ
とができる半導体装置の製造方法を提供することであ
る。
め、本発明は、ウエハをテープに貼り付け、このウエハ
の表面方向内で高速度に回転若しくは横方向に往復運動
させながら、エッチ液と接触させることによって、ウエ
ハを均一にエッチングして膜厚を極めて小さくした後、
薄くされたウエハをダイジングして複数のチップに分割
し、これら各薄いチップを、対象基板に加熱圧順次接し
て固着させるものである。
において、急速度で回転若しくは往復運動しながら、エ
ッチ液と接触されるので、極めて均一にエッチングが行
われ、凹凸や歪の発生なしに、極めて薄いウエハを得る
ことができる。
成された複数の薄いチップは、第1の基板であるテープ
上から順次分離されて、加熱および圧接されるため、チ
ップが極めて薄いにもかかわらず、割れの発生なしに上
記第2の基板上に固着することができる。特に、上記第
1の基板として軟質のテープを用いることにより、所望
のチップのみを上方に押し上げ、このチップのみを選択
的に加熱できるので、所望のチップを上記第2の基板へ
固着するのは極めて容易である。
を、導電性接着剤を介して行うことによって、ワイヤボ
ンデイングは不要になり、工程の簡略化とコストの低減
に極めて有効である。
る。 〈実施例1〉図1に示したように、薄い半導体ウエハ1
05は、枠101によって保持されたテープ(日立化成
株式会社製、HA−1506)107の上に置かれ、こ
の半導体ウエハ105は、ダイシング溝104によって
複数のチップ105´に分離されている。分離された各
チップ105´は、加熱ヘッド106によってテープ1
07の裏面から上方へ押し上げられ、接着剤103が塗
布された基板102に押しつけられて、当該基板102
に加熱接着される。この接着剤103は、有機物質と導
電性粒子の複合材料からなる異方導電性接着剤であるた
め、基板102に形成された電極(図示せず)と薄型チ
ップ105が有する電極(図示せず)は、加圧と加熱に
よって互いに電気的に接続される。なお、上記チップ1
05´は、厚さが0.1〜10μm程度で、曲げること
が可能な極めて薄いチップである。厚さが0.1μmよ
り小さいと、このチップ105´に各種半導体素子を形
成するのが困難になり、10μmより大きいと、曲げに
よって割れの生ずる恐れがある。
め、加熱ヘッド106によってテープ107を加熱しな
がら上方へ押し上げることによって、テープ107上の
上記薄いチップ105´も押し上げられ、基板102と
均一かつ安定に接着される。
ープ107は枠101によって保持され、ウエハ105
はダイシング溝104によってチップ105´に互いに
分離されている。ウエハ105の周囲304は枠101
の内側にあって、テープ107に平坦に接着されてい
る。枠101はステンレスまたはプラスチック材で形成
されている。ウエハ105の厚さは0.1から110μ
mと極めて薄いにもかかわらず、粘着剤によってテープ
107に強固に粘着されているため、ウエハ105をテ
ープ107に粘着した状態でダイシングを行っても、薄
いチップ105´がテープ107から、ばらばらに剥離
してしまうことはない。
着した後の状態を図4に示した。図4(1)は平面図、
図4(2)は断面図である。基板102の上には、位置
合わせされて薄いチップ105´が固着されている。薄
いチップ105´に形成された電極と基板102に形成
された電極は、フェースダウンボンデイングによって互
いに接続されている。しかし、ワイヤボンディングある
いは導電性ペーストによって互いに接続してもよい。
容易にできるため、半導体装置の薄型化、高機能化およ
び低コスト化が促進されて、新しい応用展開をもたらす
ことができる。
に示した薄いチップ105´と基板102の接続部を拡
大して模式的に示した断面図である。図4(3)に示し
たように、パッド405は薄いチップ105´表面の、
パッシベーション膜408が除去された部分に設けられ
ており、導電性粒子406によって、基板102の表面
上に設けられた基板電極412に接続され、互いに導通
されている。基板102とチップ105´の間には有機
フィルム409が介在して設けられており、この有機フ
ィルム409の中に導電粒子410が含まれていて、こ
の導電性粒子410によって両者間が導通される。
うに、テープ203上のチップ202は、真空チャック
201によってハンドリングされて他の基板(図示せ
ず)上へ移動される。すなわち、テープ203の上に置
かれたチップ202は、ウエハのダイシングによって形
成された個別のチップであり、突き上げピン204によ
って突き上げられたチップ202は、真空チャック20
1によって吸引されて1個ずつ順次移動される。
り、紫外線(UV)照射または加熱によって、接着性は
低下しているが、なおわずかに接着性が残っているの
で、真空チャック201と連動して動作する突き上げピ
ン204によって、チップ202はテープ203から分
離できる。しかし、この突き上げピン204によって上
方へ突き上げる従来も方法では、チップ202の厚さが
0.1から110μmと極めて薄い場合は、チップ20
2に割れが入りやすくなり、生産性が低下してしまう。
方法を示す。図5(1)に示したように、ウエハ105
は、枠101に貼られたテープ107上に粘着剤によっ
て固定されており、エッチ液ノズル501からエッチ液
502が滴下されて、ウエハ105の表面がエッチされ
る。エッチ液502としては、本実施例では水酸化カリ
ウムの水溶液(濃度40%)を用いたが、水酸化カリウ
ム以外のエッチ液を用いてもよい。
転以上の高速度で回転されるので、図5(2)に示した
ように、エッチ液502は、ウエハ105の表面上を横
方向に高速度で移動する。そのため、ウエハ105の表
面は、段差やダメージの発生なしに均一にエッチされ、
ウエハ105は薄い膜になた。
ハ105を毎分1、000往復以上の高速往復運動する
ことにより、エッチ液502はウエハ105の表面上を
横方向に高速度でに移動し、ウエハ105の表面は、段
差やダメージの発生なしに均一にエッチされ、薄膜化さ
れた。
示す工程図である。図6(1)に示したように、枠10
1に貼られたテープ107の上に、ウエハ105を固定
した後、上記実施例2に示した方法によってウエハ10
5を薄くして、図6(2)に示す断面構造を形成し、さ
らに、図6(3)に示したように、ウエハ105にダイ
シング溝104を形成し、ウエハ105を複数のチップ
105´に分割した。
02にチップ105´を位置合わせした後、加熱ヘッド
106を下から押し当てて、所望のチップ105´を加
熱加圧し、図6(5)に示したように、基板102に薄
いチップ105´を移し、接着剤103を介して固着さ
せた。各チップ105´の特性は、分割前のウエハ状態
のときに、あらかじめ測定されており、良品と不良品が
それぞれ明確となっているので、良品のチップのみを選
択的に位置合わせし、基板102に移して固着した。な
お、実施例2および3においては、テープ107として
実施例1に用いたと同じものを用いたが、それ以外の各
種テープを使用できることは、いうまでもない。
示す工程図であり、薄いチップの主面側を基板主面を対
向させて、フェースダウンボンデイングによって接合し
た例である。まず、図7(1)に示したように、第1の
枠101に貼られた第1のテープ107の上にウエハ1
05を固定し、図7(2)に示したように、上記実施例
2と同様にして、ウエハ105を薄くした。
の表面を下向きにして、第2の枠101´に貼られた第
2のテープ107´の表面に対向させて貼り合わせた。
上記第1のテープ107をウエハ105から剥離して、
ウエハ105が第2のテープ107´の表面上に形成さ
れた構造とした後、図7(4)に示したように、ウエハ
105にダイシング溝104を形成して、複数のチップ
105´に分離させた。
02に上記チップ105´を位置合わせして加熱ヘッド
106を下から押し当てて加熱加圧し、図7(6)に示
したように、基板102に薄いチップ105´を異方導
電性接着剤709を介して接着した。
のテープ107´に移された後に基板102に移され
る。そのため、半導体チップ105´の表裏が上記実施
例1の場合とは逆になって、当初のウエハ105上面
が、基板102に固着された状態でも上面になる。した
がって、本実施例では、ウエハ105を薄くした後、所
望半導体素子をウエハ105の表面に形成すれば、この
半導体素子が、基板102の表面に形成されたチップ1
05´の表面に配置される。
よって下記効果が得られる。 (1)半導体ウエハの主面に沿って移動する高速なエッ
チ液によって、ウエハが薄くされるので、膜厚が均一な
薄いウエハを容易に得ることができ、歪や欠陥が発生す
る恐れはない。
離と基板上への接着が同一の工程で行われるため、薄い
チップを割ることなしに、基板上に固着できる。
加圧して上記基板上に移すので、極めて容易かつ低コス
トで、薄いチップを基板へ実装できる。
着することにより、ワイヤボンディングなしに、各チッ
プを基板上に接続できる。
0.1から110μmと極めて薄くされるので、曲げに
強い薄いの半導体装置を実現できる。
の図、
103…接着剤、104…ダイシング溝、 105…
ウエハ、 105´…チップ、106…加熱ヘッド、
107…テープ、 107´…第2のテープ、201…
真空チャック、 202…チップ、 203…テープ、
204…突き上げピン、 304…ウエハの周囲、 4
05…パッド、406…電極間導電粒子、 408…パ
ッシベーション膜、409…有機フィルム、 410…
導電粒子、 412…基板電極、501…エッチ液ノズ
ル、 502…エッチ液。
Claims (11)
- 【請求項1】 表面に複数の半導体素子が形成された半
導体基板を準備する工程と、前記複数の半導体素子を覆
うように前記半導体基板の表面に支持膜を形成する工程
と、前記半導体基板の裏面に薬液を接触させ、前記薬液
に対して前記半導体基板を高速移動させることにより前
記半導体基板の裏面を除去して前記半導体基板の厚さを
0.1μm〜110μmの範囲まで薄膜化する工程と、
前記複数の半導体素子を含む前記薄膜化された半導体基
板を、ダイシングにより完全に切断して複数のICチッ
プに分離する工程と、配線が形成された配線基板に前記
ICチップを前記ICチップとほぼ同じ大きさの平坦な
先端部を有する加熱ヘッドを用いて圧接することによ
り、前記ICチップを前記配線基板上にフェースダウン
ボンディングにより固着する工程とを有することを特徴
とする半導体装置の製造方法。 - 【請求項2】 前記高速移動は、前記半導体基板の回転
運動であることを特徴とする請求項1記載の半導体装置
の製造方法。 - 【請求項3】 前記半導体基板は、1000回転/分以
上で回転されることを特徴とする請求項2記載の半導体
装置の製造方法。 - 【請求項4】 前記高速移動は、前記半導体基板の往復
運動であることを特徴とする請求項1記載の半導体装置
の製造方法。 - 【請求項5】 前記高速移動は、前記半導体基板の厚さ
が±5%の範囲内で均一にエッチングされる速度で行わ
れることを特徴とする請求項1記載の半導体装置の製造
方法。 - 【請求項6】 表面に複数の素子が形成された基板を準
備する工程と、前記複数の素子を覆うように前記基板の
表面にテープを貼付する工程と、前記基板の裏面に薬液
を供給し、前記薬液に対して前記基板を高速移動させる
ことにより前記基板の裏面をエッチングして前記基板の
厚さを0.1μm〜110μmの範囲まで薄膜化する工
程と、前記複数の素子を含む前記薄膜化された基板を、
ダイシングにより完全に切断して複数のICチップに分
離する工程と、配線が形成された基板に前記ICチップ
を前記ICチップとほぼ同じ大きさの平坦な先端部を有
する加熱ヘッドを用いて圧接することにより、前記IC
チップを前記配線基板にフェースダウンボンディングに
より固着する工程とを有することを特徴とする半導体装
置の製造方法。 - 【請求項7】 前記テープは軟質テープであることを特
徴とする請求項6記載の半導体装置の製造方法。 - 【請求項8】 前記テープは枠で支持されていることを
特徴とする請求項6又は7に記載の半導体装置の製造方
法。 - 【請求項9】 前記枠はリング状であることを特徴とす
る請求項8記載の半導体装置の製造方法。 - 【請求項10】 外部電極と前記外部電極よりも厚い保
護膜を有する複数の半導体素子が表面に形成された半導
体基板を準備する工程と、前記複数の半導体素子を覆う
ように前記半導体基板の表面にテープを貼付する工程
と、前記半導体基板の裏面に薬液を接触させ、前記薬液
に対して前記半導体基板を高速移動させることにより前
記半導体基板の裏面を除去して前記半導体基板の厚さを
0.1μm〜110μmの範囲まで薄膜化する工程と、
前記複数の半導体素子を含む前記半導体基板を完全に切
断して複数のICチップに分離する工程と、配線が形成
された配線基板に前記ICチップを前記ICチップとほ
ぼ同じ大きさの平坦な先端部を有する加熱ヘッドを用い
て圧接することにより、前記ICチップを前記配線基板
上にフェースダウンボンディングにより固着する工程と
を有することを特徴とする半導体装置の製造方法。 - 【請求項11】 前記保護膜は、前記外部電極の周辺に
形成されていることを特徴とする請求項10記載の半導
体装置の製造方法。
Priority Applications (15)
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JP12023695A JP3197788B2 (ja) | 1995-05-18 | 1995-05-18 | 半導体装置の製造方法 |
EP96913741A EP0828292B1 (en) | 1995-05-18 | 1996-05-14 | Manufacture of a semiconductor device |
CNB02123244XA CN100466224C (zh) | 1995-05-18 | 1996-05-14 | 半导体器件的制造方法 |
US08/952,344 US5893746A (en) | 1995-05-18 | 1996-05-14 | Semiconductor device and method for making same |
KR1019970708198A KR100606254B1 (ko) | 1995-05-18 | 1996-05-14 | 반도체장치및그제조방법 |
CN96194858A CN1098534C (zh) | 1995-05-18 | 1996-05-14 | 半导体器件的制造方法 |
PCT/JP1996/001263 WO1996036992A1 (en) | 1995-05-18 | 1996-05-14 | Semiconductor device and its manufacture |
DE69636338T DE69636338T2 (de) | 1995-05-18 | 1996-05-14 | Verfahren zur herstellung einer halbleitervorrichtung |
AU56598/96A AU718934B2 (en) | 1995-05-18 | 1996-05-14 | Semiconductor device and method for making same |
CA002221127A CA2221127A1 (en) | 1995-05-18 | 1996-05-14 | Semiconductor device and method for making same |
TW085105952A TW420867B (en) | 1995-05-18 | 1996-05-20 | Semiconductor device and the manufacturing method thereof |
US09/289,658 US6162701A (en) | 1995-05-18 | 1999-04-12 | Semiconductor device and method for making same |
JP33672099A JP3618268B2 (ja) | 1995-05-18 | 1999-11-26 | 半導体装置の製造方法 |
US09/729,191 US6514796B2 (en) | 1995-05-18 | 2000-12-05 | Method for mounting a thin semiconductor device |
US10/260,409 US6589818B2 (en) | 1995-05-18 | 2002-10-01 | Method for mounting a thin semiconductor device |
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JP12023695A JP3197788B2 (ja) | 1995-05-18 | 1995-05-18 | 半導体装置の製造方法 |
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JP33671899A Division JP2000195829A (ja) | 1999-01-01 | 1999-11-26 | 半導体装置の製造方法及びダイシング方法 |
JP33671999A Division JP3197884B2 (ja) | 1995-05-18 | 1999-11-26 | 実装方法 |
JP33672099A Division JP3618268B2 (ja) | 1995-05-18 | 1999-11-26 | 半導体装置の製造方法 |
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EP (1) | EP0828292B1 (ja) |
JP (1) | JP3197788B2 (ja) |
KR (1) | KR100606254B1 (ja) |
CN (2) | CN100466224C (ja) |
AU (1) | AU718934B2 (ja) |
CA (1) | CA2221127A1 (ja) |
DE (1) | DE69636338T2 (ja) |
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Families Citing this family (45)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6342434B1 (en) * | 1995-12-04 | 2002-01-29 | Hitachi, Ltd. | Methods of processing semiconductor wafer, and producing IC card, and carrier |
US6882030B2 (en) * | 1996-10-29 | 2005-04-19 | Tru-Si Technologies, Inc. | Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate |
KR100377033B1 (ko) * | 1996-10-29 | 2003-03-26 | 트러시 테크날러지스 엘엘시 | Ic 및 그 제조방법 |
US6498074B2 (en) | 1996-10-29 | 2002-12-24 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
US6448153B2 (en) | 1996-10-29 | 2002-09-10 | Tru-Si Technologies, Inc. | Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners |
DE19840226B4 (de) * | 1998-09-03 | 2006-02-23 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Aufbringen eines Schaltungschips auf einen Träger |
JP3447602B2 (ja) * | 1999-02-05 | 2003-09-16 | シャープ株式会社 | 半導体装置の製造方法 |
TW502458B (en) * | 1999-06-09 | 2002-09-11 | Toshiba Corp | Bonding type semiconductor substrate, semiconductor light emission element and manufacturing method thereof |
US6333208B1 (en) | 1999-07-13 | 2001-12-25 | Li Chiung-Tung | Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding |
US6350664B1 (en) | 1999-09-02 | 2002-02-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP4239352B2 (ja) | 2000-03-28 | 2009-03-18 | 株式会社日立製作所 | 電子装置の製造方法 |
US6432752B1 (en) * | 2000-08-17 | 2002-08-13 | Micron Technology, Inc. | Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages |
US20020098620A1 (en) * | 2001-01-24 | 2002-07-25 | Yi-Chuan Ding | Chip scale package and manufacturing method thereof |
US6717254B2 (en) | 2001-02-22 | 2004-04-06 | Tru-Si Technologies, Inc. | Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture |
US6589809B1 (en) * | 2001-07-16 | 2003-07-08 | Micron Technology, Inc. | Method for attaching semiconductor components to a substrate using local UV curing of dicing tape |
JP3530158B2 (ja) * | 2001-08-21 | 2004-05-24 | 沖電気工業株式会社 | 半導体装置及びその製造方法 |
KR100411256B1 (ko) * | 2001-09-05 | 2003-12-18 | 삼성전기주식회사 | 웨이퍼 연마공정 및 이를 이용한 웨이퍼 후면 처리방법 |
US6787916B2 (en) | 2001-09-13 | 2004-09-07 | Tru-Si Technologies, Inc. | Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity |
JPWO2003028072A1 (ja) * | 2001-09-20 | 2005-01-13 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US7045890B2 (en) * | 2001-09-28 | 2006-05-16 | Intel Corporation | Heat spreader and stiffener having a stiffener extension |
US7110356B2 (en) * | 2001-11-15 | 2006-09-19 | Fujitsu Limited | Pre-provisioning a light path setup |
US6624048B1 (en) * | 2001-12-05 | 2003-09-23 | Lsi Logic Corporation | Die attach back grinding |
JP4100936B2 (ja) | 2002-03-01 | 2008-06-11 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
US7535100B2 (en) * | 2002-07-12 | 2009-05-19 | The United States Of America As Represented By The Secretary Of The Navy | Wafer bonding of thinned electronic materials and circuits to high performance substrates |
US20050064679A1 (en) * | 2003-09-19 | 2005-03-24 | Farnworth Warren M. | Consolidatable composite materials, articles of manufacture formed therefrom, and fabrication methods |
US7713841B2 (en) * | 2003-09-19 | 2010-05-11 | Micron Technology, Inc. | Methods for thinning semiconductor substrates that employ support structures formed on the substrates |
US20050064683A1 (en) * | 2003-09-19 | 2005-03-24 | Farnworth Warren M. | Method and apparatus for supporting wafers for die singulation and subsequent handling |
JP4514490B2 (ja) * | 2004-03-29 | 2010-07-28 | 日東電工株式会社 | 半導体ウエハの小片化方法 |
TWI299555B (en) * | 2006-04-28 | 2008-08-01 | Taiwan Tft Lcd Ass | Semiconductor flip-chip package component and fabricating method |
JP4589265B2 (ja) * | 2006-05-22 | 2010-12-01 | パナソニック株式会社 | 半導体接合方法 |
JP4589266B2 (ja) * | 2006-05-22 | 2010-12-01 | パナソニック株式会社 | 半導体超音波接合方法 |
US8017441B2 (en) * | 2006-06-02 | 2011-09-13 | Hiachi, Ltd. | Method for manufacturing IC tag inlet |
US7851334B2 (en) * | 2007-07-20 | 2010-12-14 | Infineon Technologies Ag | Apparatus and method for producing semiconductor modules |
JP5323331B2 (ja) * | 2007-08-24 | 2013-10-23 | リンテック株式会社 | ウェハ加工用シート |
FR2943849B1 (fr) * | 2009-03-31 | 2011-08-26 | St Microelectronics Grenoble 2 | Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur |
US20110019370A1 (en) * | 2009-07-27 | 2011-01-27 | Gainteam Holdings Limited | Flexible circuit module |
US8906782B2 (en) * | 2011-11-07 | 2014-12-09 | Infineon Technologies Ag | Method of separating semiconductor die using material modification |
CN103378226A (zh) * | 2012-04-25 | 2013-10-30 | 展晶科技(深圳)有限公司 | 发光二极管的制造方法 |
US9484260B2 (en) * | 2012-11-07 | 2016-11-01 | Semiconductor Components Industries, Llc | Heated carrier substrate semiconductor die singulation method |
US9136173B2 (en) * | 2012-11-07 | 2015-09-15 | Semiconductor Components Industries, Llc | Singulation method for semiconductor die having a layer of material along one major surface |
KR20220075241A (ko) | 2014-08-05 | 2022-06-07 | 쿨리케 & 소파 네덜란드 비.브이. | 쉬운 조립을 위한 초소형 또는 초박형 개별 컴포넌트의 구성 |
US9704820B1 (en) * | 2016-02-26 | 2017-07-11 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor manufacturing method and associated semiconductor manufacturing system |
CN106549115B (zh) * | 2016-10-27 | 2018-07-20 | 武汉华星光电技术有限公司 | 异方性导电胶膜及异方性导电胶膜的剥离方法 |
US10373869B2 (en) | 2017-05-24 | 2019-08-06 | Semiconductor Components Industries, Llc | Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus |
CN111509107B (zh) * | 2020-04-24 | 2021-06-04 | 湘能华磊光电股份有限公司 | 一种将led晶圆分离n份的倒膜的方法 |
Family Cites Families (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3915784A (en) * | 1972-04-26 | 1975-10-28 | Ibm | Method of semiconductor chip separation |
DE3336606A1 (de) * | 1983-10-07 | 1985-04-25 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur mikropackherstellung |
JPH06105718B2 (ja) * | 1984-06-05 | 1994-12-21 | 日本電気株式会社 | 半導体装置及びその製造方法 |
JPH0682718B2 (ja) * | 1985-08-12 | 1994-10-19 | 日本電信電話株式会社 | 電子デバイスの試験装置およびその使用方法 |
JPS6237939U (ja) * | 1985-08-27 | 1987-03-06 | ||
US4729963A (en) * | 1986-11-21 | 1988-03-08 | Bell Communications Research, Inc. | Fabrication method for modified planar semiconductor structures |
JPH01225509A (ja) * | 1988-03-04 | 1989-09-08 | Sumitomo Electric Ind Ltd | 半導体基板の分割方法 |
JPH0715087B2 (ja) * | 1988-07-21 | 1995-02-22 | リンテック株式会社 | 粘接着テープおよびその使用方法 |
US5071787A (en) * | 1989-03-14 | 1991-12-10 | Kabushiki Kaisha Toshiba | Semiconductor device utilizing a face-down bonding and a method for manufacturing the same |
JPH0774328B2 (ja) * | 1989-09-05 | 1995-08-09 | 千住金属工業株式会社 | 電子部品の仮固定用粘着剤 |
JP2835145B2 (ja) * | 1990-05-28 | 1998-12-14 | 株式会社東芝 | 電子装置 |
DE4032397A1 (de) * | 1990-10-12 | 1992-04-16 | Bosch Gmbh Robert | Verfahren zur herstellung einer hybriden halbleiterstruktur und nach dem verfahren hergestellte halbleiterstruktur |
JP3055193B2 (ja) * | 1991-03-19 | 2000-06-26 | セイコーエプソン株式会社 | 回路の接続方法及び液晶装置の製造方法 |
US5279704A (en) * | 1991-04-23 | 1994-01-18 | Honda Giken Kogyo Kabushiki Kaisha | Method of fabricating semiconductor device |
US5143855A (en) * | 1991-06-17 | 1992-09-01 | Eastman Kodak Company | Method for making contact openings in color image sensor passivation layer |
JPH0521529A (ja) | 1991-07-16 | 1993-01-29 | Sony Corp | ボンデイング装置 |
JPH05152303A (ja) | 1991-11-26 | 1993-06-18 | Matsushita Electric Ind Co Ltd | 突起電極を有する半導体装置および突起電極形成方法ならびにその半導体装置の実装体 |
JPH06105728B2 (ja) * | 1992-02-06 | 1994-12-21 | カシオ計算機株式会社 | 半導体装置の接合方法 |
JP2994510B2 (ja) * | 1992-02-10 | 1999-12-27 | ローム株式会社 | 半導体装置およびその製法 |
JPH05283480A (ja) | 1992-04-02 | 1993-10-29 | Toshiba Corp | 電子回路部品の接続方法 |
US5517752A (en) * | 1992-05-13 | 1996-05-21 | Fujitsu Limited | Method of connecting a pressure-connector terminal of a device with a terminal electrode of a substrate |
JPH0669278A (ja) | 1992-08-18 | 1994-03-11 | Toshiba Corp | 半導体素子の接続方法 |
JPH06105728A (ja) * | 1992-09-22 | 1994-04-19 | Hino Motors Ltd | 車両用シートのヘッドレスト装置 |
US5268065A (en) | 1992-12-21 | 1993-12-07 | Motorola, Inc. | Method for thinning a semiconductor wafer |
JPH06204267A (ja) | 1993-01-08 | 1994-07-22 | Nec Yamagata Ltd | 半導体装置の製造方法 |
JPH06244095A (ja) | 1993-02-12 | 1994-09-02 | Dainippon Screen Mfg Co Ltd | 基板冷却装置 |
JPH06260531A (ja) | 1993-03-04 | 1994-09-16 | Hitachi Ltd | テープキャリア半導体装置 |
JPH06349892A (ja) | 1993-06-10 | 1994-12-22 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
US5428190A (en) * | 1993-07-02 | 1995-06-27 | Sheldahl, Inc. | Rigid-flex board with anisotropic interconnect and method of manufacture |
US5656552A (en) * | 1996-06-24 | 1997-08-12 | Hudak; John James | Method of making a thin conformal high-yielding multi-chip module |
KR102141785B1 (ko) * | 2012-05-17 | 2020-08-06 | 다우 글로벌 테크놀로지스 엘엘씨 | 입구 유동 차폐물을 갖는 하이드로클론 |
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1995
- 1995-05-18 JP JP12023695A patent/JP3197788B2/ja not_active Expired - Lifetime
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1996
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- 1996-05-14 AU AU56598/96A patent/AU718934B2/en not_active Ceased
- 1996-05-14 DE DE69636338T patent/DE69636338T2/de not_active Expired - Lifetime
- 1996-05-14 CN CN96194858A patent/CN1098534C/zh not_active Expired - Fee Related
- 1996-05-14 EP EP96913741A patent/EP0828292B1/en not_active Expired - Lifetime
- 1996-05-14 US US08/952,344 patent/US5893746A/en not_active Expired - Lifetime
- 1996-05-14 KR KR1019970708198A patent/KR100606254B1/ko not_active IP Right Cessation
- 1996-05-14 WO PCT/JP1996/001263 patent/WO1996036992A1/ja active IP Right Grant
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1999
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2000
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CA2221127A1 (en) | 1996-11-21 |
TW420867B (en) | 2001-02-01 |
KR100606254B1 (ko) | 2006-12-07 |
JPH08316194A (ja) | 1996-11-29 |
CN1514479A (zh) | 2004-07-21 |
US6589818B2 (en) | 2003-07-08 |
EP0828292B1 (en) | 2006-07-12 |
CN100466224C (zh) | 2009-03-04 |
KR19990014853A (ko) | 1999-02-25 |
DE69636338D1 (de) | 2006-08-24 |
EP0828292A1 (en) | 1998-03-11 |
CN1098534C (zh) | 2003-01-08 |
US6162701A (en) | 2000-12-19 |
AU5659896A (en) | 1996-11-29 |
US6514796B2 (en) | 2003-02-04 |
DE69636338T2 (de) | 2007-07-05 |
EP0828292A4 (en) | 2000-01-05 |
US20010000079A1 (en) | 2001-03-29 |
US20030027376A1 (en) | 2003-02-06 |
WO1996036992A1 (en) | 1996-11-21 |
AU718934B2 (en) | 2000-05-04 |
US5893746A (en) | 1999-04-13 |
CN1188563A (zh) | 1998-07-22 |
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