TW420867B - Semiconductor device and the manufacturing method thereof - Google Patents

Semiconductor device and the manufacturing method thereof Download PDF

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Publication number
TW420867B
TW420867B TW085105952A TW85105952A TW420867B TW 420867 B TW420867 B TW 420867B TW 085105952 A TW085105952 A TW 085105952A TW 85105952 A TW85105952 A TW 85105952A TW 420867 B TW420867 B TW 420867B
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Taiwan
Prior art keywords
substrate
semiconductor
wafer
manufacturing
semiconductor device
Prior art date
Application number
TW085105952A
Other languages
English (en)
Inventor
Mitsuo Usami
Kunihiro Tsubosaki
Kunihiko Nishi
Original Assignee
Hitachi Ltd
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Publication of TW420867B publication Critical patent/TW420867B/zh

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    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

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經濟部中央橾準局貝工消费合作社印裝 A7 B7五、發明説明（1 ) 〔技術之領域〕 本發明係與半導體裝置及其製造方法有關，尤與極薄 ，因彎曲應力破損之虞少，妥適於各種卡片之半導體裝置 及能穗定且低廉形成此種薄半導體裝置之半導體裝®之製 造方法有關。 〔先前之技術及問題〕 先前曾提出利用極薄之半導體裝置，形成I C卡等各 種卡片之技術，惟先前此種薄半導體裝置，因易變簿曲應 力損壤，故不易獲得實用上充分滿意之各種卡片。 薄半導體裝置之先前之組合技術，係記載於例如「 LSI— Handbook」（日本社團法人電子通信學會編株式 會社幾社，昭和59年（西元1984年）11月30發 行，第4 0 6頁〜4 1 6頁）等*該等先前之半導體裝置 之組合技術中，則使用既使進行直接手處理亦不會裂開之 具有略2 0 0 pm以上厚度之半導體製品。 如周知*減薄半導體製品之方法，應用硏磨法。但， 以硏磨法欲將半導體製品均勻，例如以5 %內加工精度加 工時，必須高精度且高再現性之半導體製品與硏磨裝置之 平行度，而此種極高之平行度，必需極高昂之裝置，故寅 用上有困難。 又，亦有模擬半導體製品硏磨之方法，惟以該方法硏 磨大面積領域時，所裔時間顯著拉長致生產性降低。 又，將半導體製品厚度，硏磨至例如〇.l#m之極 ------：---^---^----π------^ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度遑用中國國家標準（CNS ) Μ说格（2丨0Χ297公釐） 經濟部中央樣準局貝工消费合作社印裝 A7 _ B7 __五、發明説明（2 ) 薄程度時，有因硏磨產生之應力破壞形成於半導體製品表 面之電晶體等各種半導體設備遭破壞之問題。 更以上述先前之技術直接以手處理此種薄半導體晶片 時*有半導體晶片本身遭破壞之問題，難以在髙產率和低 成本下形成半導體裝置。 〔發明之目的〕 故本發明之目的在提供可解決先前技術具有之上述問 題，遭彎曲應力破壞小，可利用於各種卡片之半導體裝置 本發明之其他目的在提供可將半導體晶片厚度減薄至 0. 1〜11 Opm程度，且可將此種極薄之晶片，不致 發生開裂以手處理之半導髋之製造方法。 〔發明之方法及作用〕 爲達成上述目的，本發明之半導體裝置，係經含多數 導電性粒子於其中之有機接著劑層相對配置薄半導體晶片 與基板，更經上述導電性粒子，互以電連接設於上述半導 體晶片之上述基板側表面上之導電性膜而成之P a d，與 設於上述基板之上述半導體晶片側表面上之基板電極。 互相相對配置之薄半導體晶片與可撓性材料製基板， 因互以上述有機接著劑粘接，固定，故即使外加鸞曲應力 遭破壤之可能性彎小。 又，半導體晶片與基板間之電連接係由含於上述有機 接著劑層中之導電性粒子完成。該導電性粒子係受分別設 本紙張尺度逋用中國國家標準（CNS ) A4洗格（210X297公釐> —ς . ---------襄------1Τ------i (請先53讀背面之注意事項再填寫本頁) 經濟部中央橾隼局員工消费合作社印裝 ? 〇3b 7 ^ A7 B7五、發明説明（3 ) 於上述半導體晶片與基板互相對位置之P a d與電極問所 附加之應力變形，因以該變形之導電性粒子電接上述半導 體晶片與基板間，故可確實以電連接上述P a d與電極間 0 上述半導體晶片上，形成具有所定圖案之鈍化膜，上 述P a d設於未形成鈍化膜之部分。因P a d厚度比鈍化 膜厚度小，故有效抑制互相對之P a d與電極間存在之上 導《性粒子移至外部*因而上述P a d與電極間上述導電 性粒子確實以電連接。 又，達成本發明之其他目的之本發明之半導體之製造 方法，係將貼於帶上之半導體製品，在該製品之表面方向 內以高速旋轉或向橫方向往復運動，與蝕刻液接觸，將半 導體製品均勻蝕刻成極薄之膜厚後，分隔變薄之半導體製 品分割成複數晶片，將各該薄晶片，加熱及加壓依序固定 於基板。 因半導體製品，向該半導體製品之面內方向，急速旋 轉或往復運動，與蝕刻液接觸，故蝕刻極爲均勻，不發生 凹凸或變形，而可獲得極薄（0. 1〜llOem)之半 導體製品。 將此種極薄半導體製品分割形成小晶片之複數薄半導 體晶片，因依序自第1基板帶上分離，加熱壓接於第2基 板上，故不但可獲得極薄之半導體晶片，且不致開裂固定 於上述第2基板上。尤因使用軟質帶做爲上述第1基板， 僅所需晶片押於上方，僅選擇加熱該晶片*故極易將所需 (請先閣讀背面之注^項再填寫本页) 本紙張尺度適用中國國家榡準（CNS > A4规格（210X297公釐） 第85105952號專利申讅案 中文説明書修正頁410867 民固86年9月修正 Α7 Β7 經濟部中央標隼局員工消費合作社印製 五、發明説明（4 ) 晶片固定於上述第2基板*將上述製品分割成晶片，實用 上以切塊完成分離成各晶片之方法爲佳。 更以導電性接著劑固定上述第2基板與半導體晶片， 即無須以線連接，對工程簡化及成本之降低極爲有效。 〔實施例〕 實施例1 如第1圜所示，將薄半導體製品1 0 5配置於以框 1 0 1保持之帶子（日立化成株式會社製，Η A - 1506)107上。該半導體製品105，係以切塊溝 1 04完全切斷，分離成複數晶片1 〇5 >。 分離之各晶片105< ，以加熱頭106自帶子 1 0 7背面向上押，押緊於預先塗布接著劑1 〇 3之基板 102，加熱粘接於該基板102»因該接著劑103係 由有機物質與導電性粒子之複合材料而成之向異導電性接 著劑，故以加壓加熱經含於上述接著劑1 〇 3中之導電性 粒子互以電連接形成於基板1 〇 2之電極（未圖示）與薄 型晶片105具有之電極（Pad;未圖示）° 又，上述晶片105'爲〇 1〜ΙΙΟίίΐη程度之 極薄厚度，可彎曲*厚度小〇· 1 //τη時，將各種半導體 元件形成於該晶片1 05 —困難’而大於1 1 〇#m時’ 因有彎曲開裂之虞，故晶片105 <之厚度0· 1〜 1 1 0以m範圍_內爲宜。 又，因上述帶子1 0 7係軟質，故以加熱頭1 〇 6加 本紙張尺度適用中國國家標準^奶以4^。10^9^*)-?- " 1^—· *^ϋ I t n^i 1^1 i ^^^1 ^SJ (請先M讀背面之注意i項再填寫本頁) 42 086 7」· - 經濟部中央標車局員工消費合作社印製 五、發明説明（5 ) 熱並向上押帶子1 0 7時帶子1 0 7上之上述薄晶片 1 0 5 ^亦被押上，與置於上方之基板1 0 2均勻且穩定 粘接。 第3圖係表示第1圚之平面構造之圖，帶子1 0 7係 由環狀框1 0 1保持，製品1 0 5以切塊溝1 0 4互相分 離成複數晶片1 0 5 —。製品1 0 5之周圍3 0 4係位於 框1 0 1內側，平坦粘度於帶子1 0 7。框1 0 1係以不 銹鋼或塑膠材料形成。因製品1 0 5之厚度不但極薄至 0. 1至11 O^m，且以粘著劑牢固粘接於帶子107 ，故即使將製品1 0 5粘接於帶子1 0 7之狀態切塊，惟 薄晶片1 0 5 <不致自帶子1 0 7分散剝離。 第4圖表示將上述薄端I 0 5 >固定於基板1 0 2後 之狀態。第4圖（1 )係平面圖*第4圖（2 )係斷面IB 。將薄晶片1 0 5 >固定於基板1 0 2之所定位置。形成 於薄晶片1 0 5 —上之電極（Pad)與形成基板1 0 2 上之電極（基板電極）係互以面下連接予以連接。惟互以 線連接或導《性糊連接亦可。 因薄晶片之寅裝簡單且容易，故可促進半導體裝置之 薄型化，高機能化，及低廉化*而可將應用範用擴大至很 多新之領域。 又，第4圖（3)係擴大模式表示第4圇（1)，（ 2 )所示薄晶片1 〇 5 —與基板1 〇 2之連接部之斷面圖 ，第4圖（3 )所示，由導電性膜而成之Pa d (設於半 導體晶片之《極）4 0 5係設於薄晶片1 〇 5 **表面之鈍 (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標牟（CNS ) A4規格（2丨OX297公釐） 420867 經濟部中央標準局貝工消费合作社印製 A7 B7_五、發明説明（6 ) 化膜4 0 8去除之部分，以導竃性粒子4 0 6，連接於設 在基板1 0 2表面上之基板電極4 1 2，互相導通。在基 板1 0 2與晶片1 0 5 <間介設有機膜（有機接著劑層膜 )4 0 9，設有機膜4 0 9中含有導電粒子4 1 0，由該 導電性粒子4 1 0導通Pad 4 0 5與基板電極4 1 2間 。此時，如第4圖（3 )所示，鈍化膜4 0 9之膜厚大於 Pad 4 0 5之膜厚。因此，有效抑制介在Pad4 0 5 與基板電極4 1 2間之導電性粒子4 0 6向外部移動，結 果Pa d 4 0 5與基板霣極4 1 2間極確實以電連接。 一方面，先前之方法，係如第2圖所示，置於帶子 2 0 3上之晶片2 0 2，係由眞空夾具2 0 1操作移動至 其他基板（未圖示）上。即，置於帶子2 0 3上之晶片 2 0 2，係以製品切塊形成之個別之晶片，由上突梢 2 0 4上突之晶片2 0 2，係被眞空夾具2 0 1吸住逐一 依序移動。 帶子2 0 3塗有粘有劑，雖受紫外線（UV)照射或 加熱，接著性降低，惟因稍剩接著性，故由與眞空夾具 2 01連動動作之上突梢2 0 4 ，可自帶子2 0 3分離端 頭 2 0 2 0 惟由該上突梢2 0 4向上突出之先前之方法，在晶片 2 0 2之厚度極薄0. 1至110#111時，晶片2 0 2易 裂開，而降低生產性，故供廣泛實用困難。 實施例2 (請先鬩讀背面之注意事項再填寫本頁) 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X297公釐} 420867 ^ A7 B7 經濟部中央標準扃員工消費合作社印裝 五、發明説明（ 7 ) 1 I 本實施例 乃 減 薄 半 導 體 製 品 之 方 法 之 例 子 0 1 1 如第5圖 ( 1 ) 所 示 以 粘 著 劑 將 S 製 品 10 5 固 1 定於貼在框1 0 1 之帶 子 1 0 7 上 後 $ 以 毎 1 0 0 0 轉 以 —S ! 讀 1 I 上高速度旋轉 S • 製 品 9 由 蝕 刻 液 噴嘴 5 0 1 將 蝕刻 液 先 閱 1 I 1 5 0 2滴於上 述 S » 製 品 1 0 5 上 9 蝕 刻 S 1 製 品1 0 5 背 1 1 表面 。上述蝕 刻 液 5 0 2 在本 實 施 例 使 用 氫 氧 化鉀 之 水 之 注 意 1 I 溶液 (濃度4 0 % ) > 惟使 用 氫 氧鉀 以 外 之 蝕 刻 液亦 可 0 事 項 再 1 1 因以高速旋 轉 上 述 S * 製 品 1 0 5 滴 下 蝕 刻液 填 寫 本 裝 5 0 2，故滴於 S 1 製 品 1 0 5 表 面 上 之 蝕 刻 液 5 0 2 係 頁 1 1 如第 5圖（2 ) 所 示 Ϊ 在 S i 製 品 1 0 5 表 面 上 以高 速 度 1 1 向橫 方向移動 0 因 此 得 以 均 勻 蝕 刻 S i 製 品 1 0 5 表 面 ! ! ，不 致產生段 差 或 損 壞 > 將 S • 製 品 1 0 5 製成 薄膜 0 訂 I 又，如第 5 圇 ( 3 ) 所示 雖 將 S i 製 品 以 每 分 1 1 I 1 » 0 0 0往 復 以 上 髙速 往 復 運 動 滴 下 上 述 蝕 刻 液5 0 2 1 ! j ，惟 同樣，蝕 刻 液 5 0 2 在 S i 製 品 1 0 5 表 面 上向 橫 方 1 1 向高速移動， 而 S i 製 品 1 0 5 表面 f 仍 不 致發 生段 差 或 知卜 1 損壤 均勻蝕刻 9 予 以 薄 膜 化 0 1 1 ! 實施 例3 1 I 第6圖係 表 示 本 發 明 之 其 他 實 施 例 之 工 程 ΓΒΟ 0 1 1 1 如第6圖 ( 1 ) 所示 9 S i 製 品 1 0 5 固 定 於貼在框 1 1 10 I之帶子 1 0 7 上 後 f 以 上 述 實 施 例 2 所示 方法 9 鈾 1 1 刻， 減薄S i 製 品 1 0 5 f 形 成 第 6 圈 ( 2 ) 示 之斷面 構 1 1 造， 更如第6 圊 ( 3 ) 所 示 f 在 S 製 品 1 0 5 形成 切 塊 1 1 本紙張尺度適用中國國家標準（CNS )戍4说格（210X29?公釐） -10 - 經濟部中央樣準局貝工消费合作社印袈 ..碘 A7 B7五、發明説明（8 ) 溝1 0 4 ，將S i製品1 〇 5分割成複數晶片1 0 5 —。 其次，如第6圖（4 )所示，將所定晶片1 0 5 >定 位於基板1 0 2後，自下方貼緊加熱頭1 〇 6 ’將該晶片 1 0 S加熱，加壓於基板1 〇 2，如第6圖（5 )所示將 晶片1 0 5 '移至基板1 〇 2，以接著劑1 0 3固定。各 晶片1 0 5 #之特性，係在分割前之製品狀態時，因預先 測定分明良品與不良品*故僅選良品晶片定位，移動固定 於基板1 0 2。 又，上述實施例2及3均使用與實施例1所用帶子相 同之帶子，惟當亦可使用其他各種帶子。 實施例4 本實施例係，將薄晶片主面相對於基板主面，以面下 連接至相接合兩者之例子。 首先，如第7圖（1 )所示，以粘著劑將S i製品 1 0 5固定於貼在第1框1 〇 1之第1帶子1 0 7上後， 如第7圇（2 )所示，與上述實施例2同樣，減薄S i製 品1 0 5之厚度。 其次，如第7圖（3 )所示，將S i製品1 〇 5表面 向下，相對於貼在第2框1 0 1 >之第2帶1 0 7 —表面 ，互相粘貼兩者° 自S i製品1 〇 5剝離上述第1帶1 〇 7，成爲S i 製品1 0 5形成於第2帶1 0 7 >表面上之構造後*如第 7圖（4)所示在Si製品105形成切塊溝104 ，分 t,^,π~, h (請先閱讀背面之注意事項再填寫本頁) 本紙浪尺度逋用中國圉家樣準（CNS ) A4規格（210X297公釐） 11 ，^85i05952號專利申請案 # 中文說明書修正頁民國月呈 Ί叫 i修正 補充 經濟部中央櫺準局貝工消资合作社印策 五、發明説明（9 ) 離成複數晶片1 0 5 < · 其次，如第7圖（5)所示，將上述晶片1〇5>定 位於基板1 0 2自下方貼緊加熱頭1 〇 6加熱加壓，如第 7圖（6 )所示，以向異導電性接著劑1 0 3將薄晶片 105'粘接於基板102· 依本實施例，將晶片105 >移至第2帶107"*後 移至基板1 0 2 ·因此，S i製品1 〇 5之正反兩面與上 述實施例1相反，當初之S i製品1〇5上面，以固定於 基板1 0 2之狀態亦成爲上面。故，本實施例在減薄S i 製品1 0 5後，將所需半導體元件形成於S i製品105 表面，則該半導體元件，配置於形成在基板10 2表面之 晶片1 0 5 >表面* 〔發明之效果〕 由上述說明可知，依本發明可得下述效果· (1 )因以接著劑將極薄之半導體晶片固定於基板* 並用含於上述接著劑中之導電性粒子互以電連接設於半導 體晶片表面之P、d與設於基板表面之基板電極’故因灣 曲破損之虞少，電連接之信賴性亦高· (2 )因以沿半導體製品主面移動之高速蝕刻液’減 薄膜品厚度，故易得膜厚均匀之薄半導體’而無發生變形 成欠陷之虞。 (3)因以同一工程實施例自上述帶子剝離與基板上 之粘接，故不致使半導體晶片開製，固定於基板上。 本紙乐尺度適用中國囷家揉車（〇邓）八4说格（2】0犬：!97公釐）_ _ -- - —i I In 1 I! n ! ] 1 n i! · - *1T (請先閱讀背面之注意事項再填寫本頁) ίί λ ,Λ* 播 α7 Β7 五 '發明説明（10 ) (4 )因選擇加熱，加壓所需半導體晶片移至上述基 板上，故得以極容易且低廉，將薄晶片實裝基板° (許先閲讀背面之注意事項再填寫本頁) (5 )由以向異導電接著劑固定於基板，故無需線連 接，將各半導體晶片連接於基板上。 (6)半導體晶片厚度因成可彎曲之〇 1至110 以m之極薄厚度，故可實現強耐彎曲力之薄半導體裝置。 圖示之簡單說明： 第1圖：本發明之第1實施例之說明圖。 第2圖：先前方法之說明圚。 第3圖：說明本發明之實施例之平面圖· 第4圖（1):表示晶片與基板連接之平面圖。 第4圖（2):表示晶片與基板連接之斷面圖。 第4圖（3):表示晶片與基板連接之斷面圖。 第5圖（1)〜第5圖（3):說明本發明之第2實 施例之工程圖。 經濟部中央棵準局貝工消费合作社印製 第6圖（1)〜第6圖（5):說明本發明之第3實 施例之工程圖。 第7圖（1)〜第7圓（6):說明本發明之第4實 施例之工程圖。 本紙張尺度逍用中國國家榇率（CNS M4規格（210X297公釐） -13 -

Claims (1)

  1. η Α8 Β8 C8 D8 經濟部中夾#荜局I工消費合作社印裝 六、申請#利範圍 * 第85105952號申請專利案 中文申請專利範圍修正本 民國87年4月 1. 一種半導體裝置之製造方法，其特徵係包含保持 於第1之基板上，將形成半導體元件之半導體晶圓之表面 接觸蝕刻液，沿著上述半導體晶圓之表面，將上述蝕刻液 經由高速度之移動，將上述半導體晶圓之厚度變小的工程 ，和將厚度變小之該半導體晶圓完全加以切割，分離成複 數之晶片的工程，和向對向配置於形成前述晶片之前述半 導體元件的面之第2基板，固著前述晶片之工程者。 2. 如申請專利範圍第1項之半導體裝置之製造方法’ 其中，將上述半導體晶圓之厚度變小的工程係將該半導體 晶圓之表面，接觸至上述蝕刻液，將上述半導體晶圓在於 該半導體晶圓之平面方向內，經由旋轉加以進行者* 3. 如申請專利範圍第2項之半導體裝置之製造方法’ 其中，上述半導體晶圓係以1 000次/分以上之速度加以旋 轉者。 4. 如申請專利範圍第1項之半導體裝置之製造方法’ 其中，將上述半導體晶圓之厚度變小的工程係將該半導體 晶圓之表面，接觸至上述蝕刻液，將上述半導體晶圓在於 該半導體晶圓之平面方向內，經由往復運動加以進行者。 5. 如申請專利範圍第1項之半導體裝置之製造方法* 其中，上述第1之基板係帶子者。 6. 如申請專利範圍第5項之半導體裝置之製造方法’ (請先閱讀背面之注意事項再填寫本頁) 裝· 訂 本紙蒗尺度適用中國國家榡準（CNS )人4洗格（210X297公釐） Ί - A8 B8 C8 D8 0¾67 六、申請專利範圍 其中，上述帶子係由有機物質所成軟質帶者。 ^^1 -I ^^^1 ^^^1 ^^^1 I n . HI —^1 (讀先閱讀背面之注意事項再填寫本頁) 7. 如申請專利範圍第5項之半導體裝置之製造方法， 其中，上述帶子係支持於框體者。 8. 如申請專利範圍第7項之半導體裝置之製造方法， 其中，上述框體爲環狀者> 9. 如申請專利範圍第1項之半導體裝置之製造方法， 其中，令上述晶片自上述第1之基板分離，固著於上述第2 基板之工程係選擇性加熱所期望之上述晶片，經由對第2 基板之壓接加以進行者β 10. 如申請專利範圍第1項之半導體裝置之製造方法 ，其中，令上述晶片自上述第1之基板分離，固著於第2基 板之工程係經由設於上述帶子下之加熱頭，經由將上述晶 片推起且加熱地加以進行者。 11. 如申請專利範圍第1項之半導體裝置之製造方法 ，其中，上述晶片和上述第2之基板係經由形成於該第2之 基板表面上的黏著劑層加以固著者" Μ濟部中女標準局冥工消费合作社印製 12·如申請專利範圍第11項之半導體裝置之製造方法 ，其中，上述黏著劑係向異導電性黏著劑層者。 13. 如申請專利範圍第12項之半導體裝置之製造方法 ，其中，上述向異導電性黏著劑層係包含有機物質和導電 性粒子者。 14. 如申請專利範圍第1項之半導體裝置之製造方法 ，其中，形成於上述晶片之表面的電極’和形成於上述第 2基板的電極係經由面下接合，相互電氣性地連接者。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -2 - λ2〇86Ή 蟻 C8 D8 六、 申請專利範圍 - 1 I 15 .如 串 請 專 利 範 圍 第1項之半導體裝置之製造方法 1 1 1 其 中 ，於 令 上 述 半 導 體 晶圓之厚度變小之工程和切割厚 1 度 娛 小之該 半 導 體 晶 圓 » 分離成複數晶片之工程間，具有 | 將 厚 請 1 度變小 之 該 半 導 體 晶 圓以第3基板加以保持之工程者 先 聞 1 1 讀 1 0 背 面 1 I 16 如 串 請 專 利 範 圍 第15項之半導體裝置之製造方法 之 注 意 1 1 } 其 中 ，上 述 第 3基板係由軟質之帶子所成者。 事 項 1 | 再 1 17 如 串 請 專 利 範 圍 第1項之半導體裝置之製造方法 缜 寫 ▲ 裝 1 其 中 經 由 令 上 述 半 導 體晶圓之厚度變小之工程•上述 頁 1 I 半 導 體晶圓 之 厚 度 呈 0. I | 18 如 串 請 專 利 範 圍 第1項之半導體裝置之製造方法 1 t | ) 其 中 在 將 上 述 晶 片 固 著於上述第2基板之工程前•附 1 訂 加 在 於上述 晶 片 之 上 述 第 2基板側上形成具有所定形狀之 1 1 鈍 化 膜和較 上 述 鈍 化 膜 厚 度爲小之電極的工程者》 1 1 19 如 串 請 專 利 範 圍 第18項之半導體裝置之製造方法 1 1 其 中 上 述 電 極 係 形 成 於上述晶片之上述第2之基板側 • ¥ * ! 表 面 之上述 鈍 化 膜 未 形 成 之部分上者》 ! I 20 — 種 半 導 體 裝 置 之製造方法，其特徵係具有 1 I I 具有相 互 對 向 之 第 1主面和第2主面，於第1主面準備 1 1 形 成 複數半 導 體 元 件 之 第 1基板的工程* 1 1 和將形 成 上 述 複 數 之 半導體元件之第1主面*以第1帶 ί 1 子 加 以被覆 之 X 程 ， 1 | 和旋轉 具 有 上 述 第 1帶子之上述第1基板，直至上述第 I 1 1基板厚 度呈0 .1 β m， -1 00 Am之範圍值*令全第2之主面側 1 1 1 本紙張尺度逋用中國國家標準（CNS ) A4規格（2丨0X29*7公釐〉 -3 - 4 經濟部中央喿涑局員工消費合作社印裂 ^ r- -7 i ^ A8 B8 C8 __ D8____六、申請專利範圍 使用藥液加以蝕刻之工程， 和將薄膜化之上述第1基板之上述第2主面側的表面， 以第2帶子加以被覆之工程， 和將上述第1帶子自上述第1主面除去之工程， 和切斷薄膜化之上述第1基板，分離複數之半導體晶 片之工程， 和準備形成配線之第2基板之工程， 和相互對向形成上述半導體晶片之半導體元件之面和 形成上述第2基板之配線的面的工程， 和加熱上述半導體晶片，壓接於上述第2之基板，將 形成於上述半導體晶片之上述半導體元件的外部端子和形 成於上述第2之基板的上述配線，以向異導電性黏著劑層 電氣性連接之工程者。 21.如申請專利範圍第20項之半導髖裝置之製造方法 ，其中，切斷薄膜化之上述第1基板，分離複數之半導體 晶片之工程係經由完全切斷上述第i之基板而進行者6 22 .如申請專利範圍第20項之半導體裝置之製造方法 ，其中，上述第2之帶子係以框體支持者。 2 3.—種半導體裝置之製造方法，其特徵係具有 將形成半導體元件之第1基板之表面，以第1膜加以被 覆的工程，和自以上述第1膜被覆之上述第1基板之背面側 ，薄膜化上述第1之基板之工程， 和將薄膜化之上述第1之基板之背面，以第2膜加以被 覆的工程，和將第2基板對向配置於形成上述第1基板1之 —-1 ^^1 m I * 去之 1 m I 1 - JJ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用令國國家標準（CNS ) A4说格（2!OX297公釐） 一4 _ A8 Ββ C8 DB '申請專利範圍 上述半導體元件之面的工程， 和經由加熱頭，自上述第2膜側向上述第2基板側’壓 出上述半導體晶片，將上述半導體晶片自上述第1基板剝 離之工程者。 24 _如申請專利範團第23項之半導體裝置之製造方法 ，其中，切斷上述第1基板，分離複數之半導體晶片之工 程係經由完全切斷上述第1之基板而進行者。 25.如申請專利範圍第23項之半導體裝置之製造方法 ，其中，對上述半導體晶片之上述第2基板之固著係使用 向異導電性黏著劑加以進行者。 26· —種半導體裝置之製造方法，其特徵係具有 將形成半導體元件之第1基板之表面，以帶子被覆之 工程，和令以上述帶子被覆之上述第1基板之背面側’使 用藥液加以蝕刻，薄膜化上述第1基板之工程， 和切斷薄膜化之上述第1基板，分離複數之半導體晶 片之工程，和對向於切斷之上述第1基板，配置上述第2基 板之工程， 經濟部中央¾進局R工消费合作社印笨 —- —II 1 -I I 1 - I I . I I I- --- 1 I „ ---- (請先閱讀背面之注意事項再填寫本頁) 和經由加熱頭，自上述帶子側向上述第2基板側，壓 出上述半導體晶片，將上述半導體晶片固著於上述第2基 板之工程者。 27 .如申請專利範圍第26項之半導體裝置之製造方法 ，其中，對上述半導體晶片之上述第2基板之固著係使用 向異導電性黏著劑加以進行者。 28. 一種半導體裝置之製造方法，其特徵係具有 本紙張又度適用中國國家標準（CNS M4規格（210X297公釐） 一 5 Ά Ί AS B8 C8 D8 七、申請專利範圍 (請先閱讀背面之注項再填寫本頁) 將形成半導體元件之半導體晶圓之表面’以第1膜被 覆之工程’和令以上述第1膜所被覆之半導體晶圓之厚度 ，薄膜化至Ο.ίβιη〜之工程’ 和完全切斷薄膜化之上述半導體晶圓’分離複數之半 導體晶片之工程，和將上述半導體晶片’固著於第2基板 之工程者。 29. —種半導體裝置之製造方法’其特徵係具有 將形成半導體元件之第1基板之表面，以第1膜被覆之 工程，和令以上述第1膜所被覆之上述第1基板之厚度|薄 膜化至O.lAm〜1004Π1之工程’ 和完全切斷薄膜化之上述第1基板’分割成複數之半 導體晶片之工程， 和自上述第1膜側，使用表面平坦之平頭，壓出上述 半導體晶片，將上述半導體晶片自上述第1膜剝離之工程 者。 經漭部中央標维局員工消費合作社印家 30·—種半導體裝置之製造方法，其特徵係具有 具有相互對向之第1主面和第2主面，於第1主面準備 形成複數半導體元件之第1基板的工程， 和將形成上述複數之半導體元件之第1主面，以第1膜 加以被覆之工程， 和直至上述第1基板厚度呈O.lMm〜iQOgjn之範圍值 ，薄膜化第1之基板之工程， 和將薄膜化之上述第1基板之上述第2主面側的表面， 以第2膜加以被覆之工程， 本级Γ張尺度適用中國國家標準（CNS Τ Α4規格（210 X 297公釐） ---- -6 一 ΰ,2 OB67 A8 B8 C8 D8 、申請專利範圍 和將上述第1膜自上述第1主面除去之工程， 和切斷薄膜化之上述第1基板，分離複數之半導體晶 片之工程， 和自上述第2膜側，使用表面平坦之平頭，壓出上述 半導體晶片，將上述半導體晶片自上述第2膜剝離之工程 者。 (請先閱讀背面之注項再填寫本頁) t· Γ 經濟部中央樣笨局男二消費合作杜印製 本紙張·尺度通用中國國家標準（CNS ) A4規格（210X297公釐） -7 -
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Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6342434B1 (en) 1995-12-04 2002-01-29 Hitachi, Ltd. Methods of processing semiconductor wafer, and producing IC card, and carrier
US6448153B2 (en) 1996-10-29 2002-09-10 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US6882030B2 (en) * 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
EP2270845A3 (en) * 1996-10-29 2013-04-03 Invensas Corporation Integrated circuits and methods for their fabrication
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
DE19840226B4 (de) * 1998-09-03 2006-02-23 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Aufbringen eines Schaltungschips auf einen Träger
JP3447602B2 (ja) * 1999-02-05 2003-09-16 シャープ株式会社 半導体装置の製造方法
EP1065734B1 (en) * 1999-06-09 2009-05-13 Kabushiki Kaisha Toshiba Bonding type semiconductor substrate, semiconductor light emitting element, and preparation process thereof.
US6333208B1 (en) 1999-07-13 2001-12-25 Li Chiung-Tung Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding
US6350664B1 (en) 1999-09-02 2002-02-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
JP4239352B2 (ja) 2000-03-28 2009-03-18 株式会社日立製作所 電子装置の製造方法
US6432752B1 (en) * 2000-08-17 2002-08-13 Micron Technology, Inc. Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages
US20020098620A1 (en) * 2001-01-24 2002-07-25 Yi-Chuan Ding Chip scale package and manufacturing method thereof
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6589809B1 (en) * 2001-07-16 2003-07-08 Micron Technology, Inc. Method for attaching semiconductor components to a substrate using local UV curing of dicing tape
JP3530158B2 (ja) * 2001-08-21 2004-05-24 沖電気工業株式会社 半導体装置及びその製造方法
KR100411256B1 (ko) * 2001-09-05 2003-12-18 삼성전기주식회사 웨이퍼 연마공정 및 이를 이용한 웨이퍼 후면 처리방법
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
JPWO2003028072A1 (ja) * 2001-09-20 2005-01-13 株式会社ルネサステクノロジ 半導体装置の製造方法
US7045890B2 (en) * 2001-09-28 2006-05-16 Intel Corporation Heat spreader and stiffener having a stiffener extension
US7110356B2 (en) * 2001-11-15 2006-09-19 Fujitsu Limited Pre-provisioning a light path setup
US6624048B1 (en) * 2001-12-05 2003-09-23 Lsi Logic Corporation Die attach back grinding
JP4100936B2 (ja) 2002-03-01 2008-06-11 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US7535100B2 (en) * 2002-07-12 2009-05-19 The United States Of America As Represented By The Secretary Of The Navy Wafer bonding of thinned electronic materials and circuits to high performance substrates
US20050064683A1 (en) * 2003-09-19 2005-03-24 Farnworth Warren M. Method and apparatus for supporting wafers for die singulation and subsequent handling
US7713841B2 (en) * 2003-09-19 2010-05-11 Micron Technology, Inc. Methods for thinning semiconductor substrates that employ support structures formed on the substrates
US20050064679A1 (en) * 2003-09-19 2005-03-24 Farnworth Warren M. Consolidatable composite materials, articles of manufacture formed therefrom, and fabrication methods
JP4514490B2 (ja) * 2004-03-29 2010-07-28 日東電工株式会社 半導体ウエハの小片化方法
TWI299555B (en) * 2006-04-28 2008-08-01 Taiwan Tft Lcd Ass Semiconductor flip-chip package component and fabricating method
JP4589266B2 (ja) * 2006-05-22 2010-12-01 パナソニック株式会社 半導体超音波接合方法
JP4589265B2 (ja) * 2006-05-22 2010-12-01 パナソニック株式会社 半導体接合方法
JP4796628B2 (ja) * 2006-06-02 2011-10-19 株式会社日立製作所 Ｉｃタグ用インレットの製造方法
US7851334B2 (en) * 2007-07-20 2010-12-14 Infineon Technologies Ag Apparatus and method for producing semiconductor modules
JP5323331B2 (ja) * 2007-08-24 2013-10-23 リンテック株式会社 ウェハ加工用シート
FR2943849B1 (fr) * 2009-03-31 2011-08-26 St Microelectronics Grenoble 2 Procede de realisation de boitiers semi-conducteurs et boitier semi-conducteur
US20110019370A1 (en) * 2009-07-27 2011-01-27 Gainteam Holdings Limited Flexible circuit module
US8906782B2 (en) * 2011-11-07 2014-12-09 Infineon Technologies Ag Method of separating semiconductor die using material modification
CN103378226A (zh) * 2012-04-25 2013-10-30 展晶科技(深圳)有限公司 发光二极管的制造方法
US9484260B2 (en) * 2012-11-07 2016-11-01 Semiconductor Components Industries, Llc Heated carrier substrate semiconductor die singulation method
US9136173B2 (en) 2012-11-07 2015-09-15 Semiconductor Components Industries, Llc Singulation method for semiconductor die having a layer of material along one major surface
KR20220075241A (ko) * 2014-08-05 2022-06-07 쿨리케 & 소파 네덜란드 비.브이. 쉬운 조립을 위한 초소형 또는 초박형 개별 컴포넌트의 구성
US9704820B1 (en) * 2016-02-26 2017-07-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor manufacturing method and associated semiconductor manufacturing system
CN106549115B (zh) * 2016-10-27 2018-07-20 武汉华星光电技术有限公司 异方性导电胶膜及异方性导电胶膜的剥离方法
US10373869B2 (en) 2017-05-24 2019-08-06 Semiconductor Components Industries, Llc Method of separating a back layer on a substrate using exposure to reduced temperature and related apparatus
CN111509107B (zh) * 2020-04-24 2021-06-04 湘能华磊光电股份有限公司 一种将led晶圆分离n份的倒膜的方法

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3915784A (en) * 1972-04-26 1975-10-28 Ibm Method of semiconductor chip separation
DE3336606A1 (de) * 1983-10-07 1985-04-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zur mikropackherstellung
JPH06105718B2 (ja) * 1984-06-05 1994-12-21 日本電気株式会社 半導体装置及びその製造方法
JPH0682718B2 (ja) * 1985-08-12 1994-10-19 日本電信電話株式会社 電子デバイスの試験装置およびその使用方法
JPS6237939U (zh) * 1985-08-27 1987-03-06
US4729963A (en) * 1986-11-21 1988-03-08 Bell Communications Research, Inc. Fabrication method for modified planar semiconductor structures
JPH01225509A (ja) * 1988-03-04 1989-09-08 Sumitomo Electric Ind Ltd 半導体基板の分割方法
JPH0715087B2 (ja) * 1988-07-21 1995-02-22 リンテック株式会社 粘接着テープおよびその使用方法
US5071787A (en) * 1989-03-14 1991-12-10 Kabushiki Kaisha Toshiba Semiconductor device utilizing a face-down bonding and a method for manufacturing the same
JPH0774328B2 (ja) * 1989-09-05 1995-08-09 千住金属工業株式会社 電子部品の仮固定用粘着剤
JP2835145B2 (ja) * 1990-05-28 1998-12-14 株式会社東芝 電子装置
DE4032397A1 (de) * 1990-10-12 1992-04-16 Bosch Gmbh Robert Verfahren zur herstellung einer hybriden halbleiterstruktur und nach dem verfahren hergestellte halbleiterstruktur
JP3055193B2 (ja) * 1991-03-19 2000-06-26 セイコーエプソン株式会社 回路の接続方法及び液晶装置の製造方法
US5279704A (en) * 1991-04-23 1994-01-18 Honda Giken Kogyo Kabushiki Kaisha Method of fabricating semiconductor device
US5143855A (en) * 1991-06-17 1992-09-01 Eastman Kodak Company Method for making contact openings in color image sensor passivation layer
JPH0521529A (ja) 1991-07-16 1993-01-29 Sony Corp ボンデイング装置
JPH05152303A (ja) 1991-11-26 1993-06-18 Matsushita Electric Ind Co Ltd 突起電極を有する半導体装置および突起電極形成方法ならびにその半導体装置の実装体
JPH06105728B2 (ja) * 1992-02-06 1994-12-21 カシオ計算機株式会社 半導体装置の接合方法
JP2994510B2 (ja) * 1992-02-10 1999-12-27 ローム株式会社 半導体装置およびその製法
JPH05283480A (ja) 1992-04-02 1993-10-29 Toshiba Corp 電子回路部品の接続方法
US5517752A (en) * 1992-05-13 1996-05-21 Fujitsu Limited Method of connecting a pressure-connector terminal of a device with a terminal electrode of a substrate
JPH0669278A (ja) 1992-08-18 1994-03-11 Toshiba Corp 半導体素子の接続方法
JPH06105728A (ja) * 1992-09-22 1994-04-19 Hino Motors Ltd 車両用シートのヘッドレスト装置
US5268065A (en) * 1992-12-21 1993-12-07 Motorola, Inc. Method for thinning a semiconductor wafer
JPH06204267A (ja) 1993-01-08 1994-07-22 Nec Yamagata Ltd 半導体装置の製造方法
JPH06244095A (ja) 1993-02-12 1994-09-02 Dainippon Screen Mfg Co Ltd 基板冷却装置
JPH06260531A (ja) 1993-03-04 1994-09-16 Hitachi Ltd テープキャリア半導体装置
JPH06349892A (ja) 1993-06-10 1994-12-22 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5428190A (en) * 1993-07-02 1995-06-27 Sheldahl, Inc. Rigid-flex board with anisotropic interconnect and method of manufacture
US5656552A (en) * 1996-06-24 1997-08-12 Hudak; John James Method of making a thin conformal high-yielding multi-chip module
CA2872516C (en) * 2012-05-17 2020-09-22 Dow Global Technologies Llc Hydroclone with inlet flow shield

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CN1188563A (zh) 1998-07-22
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US6514796B2 (en) 2003-02-04
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CN100466224C (zh) 2009-03-04
US6162701A (en) 2000-12-19
US20010000079A1 (en) 2001-03-29
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AU5659896A (en) 1996-11-29
US5893746A (en) 1999-04-13
US20030027376A1 (en) 2003-02-06
CN1098534C (zh) 2003-01-08
JP3197788B2 (ja) 2001-08-13
US6589818B2 (en) 2003-07-08
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WO1996036992A1 (en) 1996-11-21
DE69636338T2 (de) 2007-07-05

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