JP2020038982A - 配線構造体 - Google Patents
配線構造体 Download PDFInfo
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- JP2020038982A JP2020038982A JP2019201643A JP2019201643A JP2020038982A JP 2020038982 A JP2020038982 A JP 2020038982A JP 2019201643 A JP2019201643 A JP 2019201643A JP 2019201643 A JP2019201643 A JP 2019201643A JP 2020038982 A JP2020038982 A JP 2020038982A
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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Abstract
Description
図1は、本発明の一実施形態に係る配線構造体の断面図を示す。図1においては、第1層(下層)の配線と第2層(上層)の配線とを接続するための接続孔の断面も含まれている。接続孔は、第1層の配線と第2層の配線とが重畳する領域に配置される。なお、接続孔に配置される第2層の配線の部分をビア接続部という場合がある。
図4は、本発明の実施形態2に係る配線構造体を用いたLSIチップの配置の一例を示す。これは、いわゆる2.5次元実装と呼ばれる配置の一例である。
図8(a)は、本発明の実施形態3に係る配線構造体を用いたLSIチップの配置を示す。これは、いわゆる3次元実装と呼ばれる配置の一例である。
図11は、実施例3にて説明した工程により配線構造体を作成したSiインターポーザーについて、熱サイクル試験を実施したときの不良率を示すグラフである。この熱サイクル試験においては、Siインターポーザーの上面及び下面のそれぞれに、ビア接続部を介した4層からなるスタックビアチェーン(チェーン数:1000)を用いた。−25℃から125℃の温度サイクルを3000回繰り返し、チェーン抵抗が20%以上上昇したとき、その配線構造体は不良である判定した。
Claims (1)
- 第1の配線と、
第2の配線と、
前記第2の配線と前記第1の配線との間に設けられ、前記第2の配線の表面のうち少なくとも前記第1の配線の側の面を覆う無機材料膜と、前記無機材料膜を覆う第1の有機樹脂材料膜と、前記第1の有機樹脂材料膜上に設けられた第2の有機樹脂材料膜を含む第1の絶縁膜と、
前記第2の配線と前記第1の配線との間に設けられ、前記第1の有機樹脂材料膜と前記第2の有機樹脂材料膜との間に設けられた第3の配線と、
を備える、多層配線構造体。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2021109577A JP7188502B2 (ja) | 2012-11-05 | 2021-06-30 | 多層配線構造体とその製造方法 |
JP2022190661A JP7452605B2 (ja) | 2012-11-05 | 2022-11-29 | 多層配線構造体とその製造方法 |
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JP2012243593 | 2012-11-05 | ||
JP2012243593 | 2012-11-05 | ||
JP2017150462A JP6614212B2 (ja) | 2012-11-05 | 2017-08-03 | 配線構造体 |
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JP2017150462A Division JP6614212B2 (ja) | 2012-11-05 | 2017-08-03 | 配線構造体 |
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JP2021109577A Division JP7188502B2 (ja) | 2012-11-05 | 2021-06-30 | 多層配線構造体とその製造方法 |
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JP2020038982A true JP2020038982A (ja) | 2020-03-12 |
JP6908090B2 JP6908090B2 (ja) | 2021-07-21 |
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JP2014544625A Active JP6435860B2 (ja) | 2012-11-05 | 2013-11-05 | 配線構造体 |
JP2016083558A Active JP6249043B2 (ja) | 2012-11-05 | 2016-04-19 | 配線構造体 |
JP2017150462A Active JP6614212B2 (ja) | 2012-11-05 | 2017-08-03 | 配線構造体 |
JP2019201643A Active JP6908090B2 (ja) | 2012-11-05 | 2019-11-06 | 配線構造体 |
JP2021109577A Active JP7188502B2 (ja) | 2012-11-05 | 2021-06-30 | 多層配線構造体とその製造方法 |
JP2022190661A Active JP7452605B2 (ja) | 2012-11-05 | 2022-11-29 | 多層配線構造体とその製造方法 |
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JP2014544625A Active JP6435860B2 (ja) | 2012-11-05 | 2013-11-05 | 配線構造体 |
JP2016083558A Active JP6249043B2 (ja) | 2012-11-05 | 2016-04-19 | 配線構造体 |
JP2017150462A Active JP6614212B2 (ja) | 2012-11-05 | 2017-08-03 | 配線構造体 |
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JP2021109577A Active JP7188502B2 (ja) | 2012-11-05 | 2021-06-30 | 多層配線構造体とその製造方法 |
JP2022190661A Active JP7452605B2 (ja) | 2012-11-05 | 2022-11-29 | 多層配線構造体とその製造方法 |
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US (7) | US9735108B2 (ja) |
JP (6) | JP6435860B2 (ja) |
WO (1) | WO2014069662A1 (ja) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2014069662A1 (ja) * | 2012-11-05 | 2014-05-08 | 大日本印刷株式会社 | 配線構造体 |
US20160086960A1 (en) | 2014-09-22 | 2016-03-24 | Texas Instruments Incorporated | Low-Temperature Passivation of Ferroelectric Integrated Circuits for Enhanced Polarization Performance |
US9564396B2 (en) * | 2014-09-26 | 2017-02-07 | Taiwan Semiconductor Manufucturing Company, Ltd. | Semiconductor device and process |
JP6361464B2 (ja) * | 2014-10-24 | 2018-07-25 | 富士通株式会社 | 配線構造 |
JP6589277B2 (ja) * | 2015-01-14 | 2019-10-16 | 富士電機株式会社 | 高耐圧受動素子および高耐圧受動素子の製造方法 |
JP2017034155A (ja) * | 2015-08-04 | 2017-02-09 | 大日本印刷株式会社 | 表示装置 |
JP6908154B2 (ja) * | 2015-10-28 | 2021-07-21 | 大日本印刷株式会社 | インターポーザ及びインターポーザの製造方法 |
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