JP2019212891A - 膜、マルチレベル素子、マルチレベル素子の製造方法、マルチレベル素子の駆動方法 - Google Patents
膜、マルチレベル素子、マルチレベル素子の製造方法、マルチレベル素子の駆動方法 Download PDFInfo
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Abstract
Description
によって、前記第2のアクティブ層の活性化がシールドされてもよい。
電極120に印加される場合、前記第1のアクティブ層150を流れる電流の量が飽和(saturation)されたことを意味する。すなわち、第2のゲート電圧範囲R2では、ゲート電圧が増加しても電流が保持されるという点で、仲介(intermediate)電圧範囲であると理解されてもよい。
of state)を説明するための図であり、図8は、結晶質、非晶質、本発明の一実施形態に係るアクティブ層のDOS(density of state)を説明するための図であり、図9は、本発明の一実施形態に係る波動関数を説明するための図であり、図10は、本発明の一実施形態に係るマルチレベル素子をエネルギーバンドの観点から説明するための図である。
制限された電流の移動を提供することができる。前記量子化された伝導性状態について図7及び図8aに基づいてより詳細に説明する。
、第1のゲート電圧範囲から第5のゲート電圧範囲(R1〜R5)を提供することができる。すなわち、前記第2及び第4のゲート電圧範囲(R2、R4)において、量子化された伝導性状態による飽和電流が発生することができ、前記第5のゲート電圧範囲R5において、第3のアクティブ層174とソース/ドレイン電極180、185の接触によって電流は増加することができる。
段階S110は、事前用意の段階であって、基板を用意する段階と、基板上にゲート電極を形成する段階と、前記ゲート電極上にゲート絶縁膜を形成する段階と、を含んでいてもよい。
段階S120において第1のアクティブ層150が蒸着されてもよい。図16に基づいて段階S120を具体的に説明する。
ソースガス加圧ドージング段階(S210)のために、ソースガスが用意されてもよい。ソースガスは、蒸着しようとする膜の種類に応じて種々に用意されてもよい。例えば、蒸着しようとする膜が金属酸化物である場合、それに対応する金属前駆体ソースガスが用意されてもよい。例えば、蒸着しようとする膜がジンクオキサイド(ZnO)である場合、ソースガスは、DEZ(diethyl zinc)を含んでいてもよい。
第1のメインパージング段階(S220)において、不活性ガスが用いられてもよく、不活性ガスは、例えば、アルゴン(Ar)、または窒素(N2)ガスからなってもよい。パージングする段階によって、基板の表面に吸着し切れなかった過剰のソースガスが除去可能である。
反応ガスドージング段階(S230)において、反応ガスは、ソースガスと反応して蒸着しようとする膜に還元されてもよい。例えば、ソースガスがDEZを含む場合、反応ガスはH2Oからなってもよい。
反応ガスドージング段階後に、第2のメインパージング段階(S240)がさらに行われてもよい。これにより、基板の表面に吸着し切れなかった過剰のガスが除去可能になる。
段階S210のソースガス加圧ドージング段階は、加圧雰囲気下で行われてもよい。換言すれば、ソースガス加圧ドージング段階は、高圧の雰囲気下で行われてもよく、これは加圧段階と略称することがある。
加圧ドージング段階によって提供された所定の圧力を保持する段階である。このために、チャンバーの流入口及び流出口が両方とも閉じられてもよい。すなわち、チャンバーは密閉されてもよい。前記サブパージング段階は、前記サブ露出段階後に行われて、過剰に供給されたソースガスを除去することができる。
再び図15を参照すると、第1のアクティブ層150上に第2のバリア層160が蒸着されてもよい。段階S130は、前述した段階S110に対応するので、具体的な説明を省略する。
第2のバリア層160上に第2のアクティブ層170が蒸着されてもよい。このとき、段階S140は、前述した段階S120に対応するので、具体的な説明を省略する。
実験例によるマルチレベル素子を作製するために、まず、基板として300nmの厚さのシリコンウェハを用意し、シリコンウェハ上に70nm厚のアルミニウムゲート電極を蒸着した。ゲート電極の蒸着に際しては、熱気相蒸着により蒸着させた。ゲート電極上に絶縁膜として酸化アルミニウム(Al2O3)を蒸着した。酸化アルミニウムは、原子層蒸着工程を用いて蒸着され、TMA前駆体ソースガス提供段階、パージ段階、H2O提供段階、パージ段階の順で進められた。酸化アルミニウムの厚さを、蒸着されるアクティブ層の層数に応じて異ならせた。酸化アルミニウムの厚さを、アクティブ層の層数が増加するほど厚くした。
Claims (19)
- ゲート電極と、
前記ゲート電極の一方の側に形成される第1のアクティブ層と、
前記第1のアクティブ層の一方の側に形成される第2のアクティブ層と、
ソース及びドレイン電極と、
前記第1のアクティブ層と前記第2のアクティブ層とを分離するバリア層と、を含み、
前記ゲート電極に印加されるゲート電圧の大きさに応じて、前記第1及び前記第2のアクティブ層のうちチャネルが形成されるアクティブ層の数が制御される、マルチレベル素子。 - 前記第1のアクティブ層と前記ゲート電極との距離は、前記第2のアクティブ層と前記ゲート電極との距離よりも短い、請求項1に記載のマルチレベル素子。
- 前記ゲート電圧は、第1のゲート電圧範囲、前記第2のゲート電圧範囲及び前記第3のゲート電圧範囲に区分されるが、
前記ゲート電圧の増加順に従って前記第1、第2及び第3のゲート電圧範囲が提供される、請求項2に記載のマルチレベル素子。 - 前記ゲート電極に前記第1のゲート電圧範囲内のゲート電圧が印加される場合、前記第1のアクティブ層のみが活性化され、
前記ゲート電極に前記第3のゲート電圧範囲内のゲート電圧が印加される場合、前記第1及び前記第2のアクティブ層が活性化される、請求項3に記載のマルチレベル素子。 - 前記ゲート電極に前記第2のゲート電圧範囲内のゲート電圧が印加される場合、前記第1のアクティブ層のみが活性化されるが、
前記第2のゲート電圧の範囲内におけるゲート電圧の増加による、第1のアクティブ層を流れる電流の増加は、第1のゲート電圧の範囲内におけるゲート電圧の増加による、第1のアクティブ層を流れる電流の増加よりも少ない、請求項4に記載のマルチレベル素子。 - 前記第2のゲート電圧の範囲内でゲート電圧が増加しても、前記第1のアクティブ層を流れる電流の量は一定に保持される、請求項5に記載のマルチレベル素子。
- 前記第2のゲート電圧の範囲内における前記第1のアクティブ層は、飽和状態(saturation state)である、請求項5に記載のマルチレベル素子。
- 前記ゲート電極に前記第2のゲート電圧範囲のゲート電圧が印加された場合、前記第1のアクティブ層に流れる電流によって前記ゲート電極から前記第2のアクティブ層に加えられるフィールドが遮蔽される、請求項3に記載のマルチレベル素子。
- ソース電極及びドレイン電極をさらに含み、
前記ソース電極及び前記ドレイン電極は、前記第1及び前記第2のアクティブ層のうちのいずれか一方のアクティブ層とのみ接触する、請求項1に記載のマルチレベル素子。 - ソース電極及びドレイン電極をさらに含み、
前記ソース電極及び前記ドレイン電極は、前記第1及び前記第2のアクティブ層と接触しない、請求項1に記載のマルチレベル素子。 - 前記ゲート電極と前記第1のアクティブ層との間のバリア層をさらに含み、
前記ゲート電極と前記第1のアクティブ層との間のバリア層、第1のアクティブ層及び前記第1のアクティブ層と前記第2のアクティブ層とを分離するバリア層は、量子井戸(quantum well)を形成する、請求項1に記載のマルチレベル素子。 - 前記第1及び前記第2のアクティブ層のうちの少なくとも1つのアクティブ層は、伝導帯(conduction band)内の低レベル電子エネルギー範囲で第1の電子状態の数を提供し、前記伝導帯内の、前記低レベル電子エネルギー範囲よりも高い高レベル電子エネルギー範囲で第2の電子状態の数を提供し、
前記低レベル電子エネルギー範囲と前記高レベル電子エネルギー範囲との間で偏在状態を提供する、請求項1に記載のマルチレベル素子。 - 前記低レベル電子エネルギー範囲における電子状態の数が最大である電子エネルギー値を基準として、前記第1の電子状態の数は、正規分布される、請求項12に記載のマルチレベル素子。
- 前記第1及び前記第2のアクティブ層のうちの少なくとも1つのアクティブ層は、非晶質領域及び前記非晶質領域によって取り囲まれる複数の結晶質領域を含み、
前記非晶質領域が有する第1のエネルギー状態のうちの特定の第1のエネルギー状態と前記結晶質領域が有する第2のエネルギー状態のうちの特定の第2のエネルギー状態とのマッチング(matching)によって量子化された伝導性状態を提供する、請求項1に記載のマルチレベル素子。 - 前記量子化された伝導性状態は、前記ゲート電極に印加されるゲート電圧範囲が所定の範囲である場合、前記ソース及び前記ドレイン電極間に制限された電流の移動を許容する、請求項14に記載のマルチレベル素子。
- チャンバー内に基板を用意した状態で、前記基板上に、第1のアクティブ層形成段階と、
バリア層形成段階と、
第2のアクティブ層形成段階と、を含み、
前記第1のアクティブ層形成段階及び前記第2のアクティブ層形成段階のうちの少なくとも1つの段階は、
前記チャンバーの流出口を閉じた状態で、金属前駆体を有する金属前駆体ソースガスを提供することにより、前記チャンバー内の圧力を増加させて、前記金属前駆体を前記基板に吸着させるソースガス加圧ドージング(dosing)段階と、
前記ソースガス加圧ドージング段階後に、パージさせる第1のメインパージング(main purging)段階と、
前記第1のメインパージング段階後に、反応ガスを提供する反応ガスドージング段階と、
前記反応ガスドージング段階後に、パージさせる第2のメインパージング段階と、を含む、マルチレベル素子の製造方法。 - ゲート電極に、第1のゲート電圧範囲のゲート電圧を印加して、第1のアクティブ層を活性化させる第1の段階と、
前記ゲート電極に、前記第1のゲート電圧範囲のゲート電圧よりも大きい第2のゲート電圧範囲のゲート電圧を印加する第2段階と、
前記ゲート電極に、前記第2のゲート電圧範囲のゲート電圧よりも大きい第3のゲート電圧範囲のゲート電圧を印加して、第1及び第2のアクティブ層を活性化させる第3の段階と、を含む、マルチレベル素子の駆動方法。 - 前記第2の段階において、
前記第1のアクティブ層は、活性化状態を保持し、
前記第2のアクティブ層は、非活性化状態である、請求項17に記載のマルチレベル素子の駆動方法。 - 前記第2の段階において、
前記第1のアクティブ層に流れる電流によって、前記第2のアクティブ層の活性化がシールドされる、請求項17に記載のマルチレベル素子の駆動方法。
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CN111192914B (zh) | 2023-10-31 |
EP3608970A1 (en) | 2020-02-12 |
CN110741478A (zh) | 2020-01-31 |
CN110741478B (zh) | 2023-08-29 |
CN111435681B (zh) | 2023-10-27 |
US10991831B2 (en) | 2021-04-27 |
JP6868907B2 (ja) | 2021-05-12 |
EP3640993A1 (en) | 2020-04-22 |
JP6860931B2 (ja) | 2021-04-21 |
KR102196005B1 (ko) | 2020-12-30 |
JP6836604B2 (ja) | 2021-03-03 |
CN111435681A (zh) | 2020-07-21 |
US20190214291A1 (en) | 2019-07-11 |
JP2019208002A (ja) | 2019-12-05 |
EP3651203A1 (en) | 2020-05-13 |
KR20190043490A (ko) | 2019-04-26 |
KR102250003B1 (ko) | 2021-05-11 |
JP2019537235A (ja) | 2019-12-19 |
CN111192914A (zh) | 2020-05-22 |
KR20190043491A (ko) | 2019-04-26 |
EP3608970A4 (en) | 2020-11-25 |
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