JP2018133533A - リードフレーム及びその製造方法 - Google Patents
リードフレーム及びその製造方法 Download PDFInfo
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- JP2018133533A JP2018133533A JP2017028222A JP2017028222A JP2018133533A JP 2018133533 A JP2018133533 A JP 2018133533A JP 2017028222 A JP2017028222 A JP 2017028222A JP 2017028222 A JP2017028222 A JP 2017028222A JP 2018133533 A JP2018133533 A JP 2018133533A
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- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- 239000002184 metal Substances 0.000 claims abstract description 52
- 238000000034 method Methods 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 3
- 239000011347 resin Substances 0.000 description 12
- 229920005989 resin Polymers 0.000 description 12
- 238000007789 sealing Methods 0.000 description 12
- 239000004065 semiconductor Substances 0.000 description 12
- 238000005530 etching Methods 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 9
- 239000010931 gold Substances 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000010949 copper Substances 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 3
- 229910052763 palladium Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910000640 Fe alloy Inorganic materials 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- VUCAVCCCXQVHAN-UHFFFAOYSA-L azane dichlorocopper Chemical compound N.Cl[Cu]Cl VUCAVCCCXQVHAN-UHFFFAOYSA-L 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 230000007723 transport mechanism Effects 0.000 description 1
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Abstract
【解決手段】リードフレームは、矩形状の外枠の外端部10aと、外枠の外端部10aの上面S1から側面S3にかけて形成された第1凹部C1と、外枠の外端部10aの下面S2から側面S3にかけて形成された第2凹部C2とを含み、第1凹部C1及び第2凹部C2の各側壁と側面S3とが接する部分がそれぞれ曲面状に形成されている。これにより、リードフレームの外枠の側面の直角部分を少なくすることができる。
【選択図】図4
Description
図2〜図7は実施形態のリードフレームを説明するための図、図8〜図12は実施形態のリードフレームの製造方法を説明するための図である。
各製品領域Rの中央部には四角状のダイパッド20が配置されている。また、ダイパッド20の四隅にサポートバー22がそれぞれ繋がっており、サポートバー22は外枠10及び内枠12に連結されている。
Claims (10)
- 矩形状の外枠と、
前記外枠の上面から側面にかけて形成された第1凹部と、
前記外枠の下面から側面にかけて形成された第2凹部と
を有し、
前記第1凹部及び前記第2凹部の各側壁と側面とが接する部分がそれぞれ曲面状であることを特徴とするリードフレーム。 - 前記第1凹部及び前記第2凹部は、所定の間隔を空けて並んで配置されており、前記第1凹部は平面視で前記第2凹部の間に配置されていることを特徴とする請求項1に記載のリードフレーム。
- 前記第1凹部同士の間の前記側面の上端、及び前記第2凹部同士の間の前記側面の下端は、平面視でそれぞれ平坦部となっていることを特徴とする請求項2に記載のリードフレーム。
- 前記第1凹部及び前記第2凹部は、前記外枠の長手方向の両側の前記側面にそれぞれ形成されていることを特徴とする請求項1乃至3のいずれか一項に記載のリードフレーム。
- 前記第1凹部及び前記第2凹部の各内面及び前記側面は、凹状曲面となって形成されることを特徴とする請求項1乃至4のいずれか一項に記載のリードフレーム。
- 複数のフレーム領域が区画された金属板を用意する工程と、
前記金属板の両面側の前記フレーム領域に、フレーム部材を得るためのレジスト層をそれぞれパターニングする工程と、
前記レジスト層をマスクにして前記金属板を両面側からウェットエッチングすることにより、矩形状の外枠と、前記外枠の上面から側面にかけて形成される第1凹部と、前記外枠の下面から側面にかけて形成される第2凹部とを含むフレーム部材を前記複数のフレーム領域に形成する工程と、
前記レジスト層を除去する工程と、
前記複数のフレーム領域に配置された前記フレーム部材を分離して、個々のリードフレームを得る工程とを有し、
前記第1凹部及び前記第2凹部の各側壁と前記側面とが接する部分がそれぞれ曲面状に形成されることを特徴とするリードフレームの製造方法。 - 前記レジスト層を形成する工程において、
前記レジスト層は、外枠パターンと、前記外枠パターンの側面に配置された切欠部とを含み、前記第1凹部及び前記第2凹部は前記レジスト層の切欠部に対応して形成され、
平面視で前記切欠部の側壁と前記外枠パターンの側面とが接する角度が90°を超えて135°以下に設定されることを特徴とする請求項6に記載のリードフレームの製造方法。 - 前記フレーム部材を形成する工程において、
前記第1凹部及び前記第2凹部は、所定の間隔を空けて並んで配置され、前記第1凹部は平面視で前記第2凹部の間に配置されることを特徴とする請求項6又は7に記載のリードフレームの製造方法。 - 前記フレーム部材を形成する工程において、
前記第1凹部同士の間の側面の上端、及び前記第2凹部同士の間の側面の下端が、平面視でそれぞれ平坦部となって形成されることを特徴とする請求項6乃至8のいずれか一項に記載のリードフレームの製造方法。 - 前記フレーム部材を形成する工程において、
前記第1凹部及び前記第2凹部は、前記外枠の長手方向の両側の前記側面にそれぞれ形成されることを特徴とする請求項6乃至9のいずれか一項に記載のリードフレームの製造方法。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080258272A1 (en) * | 2007-04-19 | 2008-10-23 | Lay Yeap Lim | Etched leadframe structure |
JP2013058693A (ja) * | 2011-09-09 | 2013-03-28 | Dainippon Printing Co Ltd | 半導体素子用リードフレーム、樹脂付半導体素子用リードフレームおよび半導体装置、並びに、半導体素子用リードフレームの製造方法、樹脂付半導体素子用リードフレームの製造方法および半導体装置の製造方法 |
JP2015072946A (ja) * | 2013-10-01 | 2015-04-16 | 大日本印刷株式会社 | リードフレームおよびその製造方法、ならびに半導体装置の製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4400714A (en) * | 1980-11-06 | 1983-08-23 | Jade Corporation | Lead frame for semiconductor chip |
US6661083B2 (en) | 2001-02-27 | 2003-12-09 | Chippac, Inc | Plastic semiconductor package |
JP2004319816A (ja) | 2003-04-17 | 2004-11-11 | Fujitsu Ltd | リードフレーム及びその製造方法 |
JP2010129591A (ja) * | 2008-11-25 | 2010-06-10 | Mitsui High Tec Inc | リードフレーム、このリードフレームを用いた半導体装置及びその中間製品、並びにこれらの製造方法 |
JP4764519B1 (ja) * | 2010-01-29 | 2011-09-07 | 株式会社東芝 | Ledパッケージ |
JP2011165833A (ja) * | 2010-02-08 | 2011-08-25 | Toshiba Corp | Ledモジュール |
US20120126378A1 (en) * | 2010-11-24 | 2012-05-24 | Unisem (Mauritius ) Holdings Limited | Semiconductor device package with electromagnetic shielding |
US8723324B2 (en) * | 2010-12-06 | 2014-05-13 | Stats Chippac Ltd. | Integrated circuit packaging system with pad connection and method of manufacture thereof |
JP6078948B2 (ja) * | 2012-01-20 | 2017-02-15 | 日亜化学工業株式会社 | 発光装置用パッケージ成形体及びそれを用いた発光装置 |
US8674487B2 (en) * | 2012-03-15 | 2014-03-18 | Advanced Semiconductor Engineering, Inc. | Semiconductor packages with lead extensions and related methods |
US9013028B2 (en) * | 2013-01-04 | 2015-04-21 | Texas Instruments Incorporated | Integrated circuit package and method of making |
DE102014102184A1 (de) * | 2014-02-20 | 2015-08-20 | Osram Opto Semiconductors Gmbh | Herstellung eines optoelektronischen Bauelements |
JP6387787B2 (ja) * | 2014-10-24 | 2018-09-12 | 日亜化学工業株式会社 | 発光装置、パッケージ及びそれらの製造方法 |
JP6168096B2 (ja) * | 2015-04-28 | 2017-07-26 | 日亜化学工業株式会社 | 発光装置、パッケージ及びそれらの製造方法 |
JP6455932B2 (ja) * | 2015-06-16 | 2019-01-23 | 大口マテリアル株式会社 | Ledパッケージ及び多列型led用リードフレーム、並びにそれらの製造方法 |
JP2017103365A (ja) * | 2015-12-02 | 2017-06-08 | 新光電気工業株式会社 | リードフレーム及び電子部品装置とそれらの製造方法 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20080258272A1 (en) * | 2007-04-19 | 2008-10-23 | Lay Yeap Lim | Etched leadframe structure |
CN101299425A (zh) * | 2007-04-19 | 2008-11-05 | 费查尔德半导体有限公司 | 蚀刻引线框结构 |
JP2013058693A (ja) * | 2011-09-09 | 2013-03-28 | Dainippon Printing Co Ltd | 半導体素子用リードフレーム、樹脂付半導体素子用リードフレームおよび半導体装置、並びに、半導体素子用リードフレームの製造方法、樹脂付半導体素子用リードフレームの製造方法および半導体装置の製造方法 |
JP2015072946A (ja) * | 2013-10-01 | 2015-04-16 | 大日本印刷株式会社 | リードフレームおよびその製造方法、ならびに半導体装置の製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021068753A (ja) * | 2019-10-18 | 2021-04-30 | 大日本印刷株式会社 | リードフレーム、リードフレームの製造方法及び半導体装置の製造方法 |
JP7404763B2 (ja) | 2019-10-18 | 2023-12-26 | 大日本印刷株式会社 | リードフレーム、リードフレームの製造方法及び半導体装置の製造方法 |
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