JP5618285B2 - リードレス表面実装型の半導体装置の製造に用いる半導体素子搭載用基板 - Google Patents
リードレス表面実装型の半導体装置の製造に用いる半導体素子搭載用基板 Download PDFInfo
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- JP5618285B2 JP5618285B2 JP2010007023A JP2010007023A JP5618285B2 JP 5618285 B2 JP5618285 B2 JP 5618285B2 JP 2010007023 A JP2010007023 A JP 2010007023A JP 2010007023 A JP2010007023 A JP 2010007023A JP 5618285 B2 JP5618285 B2 JP 5618285B2
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- semiconductor element
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- 239000002184 metal Substances 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 238000000465 moulding Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 description 34
- 229920005989 resin Polymers 0.000 description 22
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- 238000007789 sealing Methods 0.000 description 21
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- 238000007747 plating Methods 0.000 description 7
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- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005452 bending Methods 0.000 description 5
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- 238000005520 cutting process Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 229910000531 Co alloy Inorganic materials 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 2
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- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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Description
図11は、従来のリードレス表面実装型の半導体装置の製造方法を示す断面図である。図11(A)において、厚さが0.1〜0.5mmのステンレスや銅等の導電性金属板から成るベース基板1に、プレスやエッチング等によってパイロットホール3を形成する(パイロットホールは図示せず、図7参照)。このパイロットホール3は、この後の工程において位置合わせ基準として使用される。
本発明は、短冊状シートで取り扱われる半導体素子搭載用基板において、導電性金属板からなるベース基板1の半導体素子搭載領域2の外周縁領域に、ベース基板1をプレス成形して形成された突起部4,5を備える半導体素子搭載用基板である。突起部によって、ベース基板の耐折性が向上し、半導体素子搭載用基板の反りを抑制することが可能となる。
図4は、本発明の一実施例に係るリードレス表面実装型の半導体装置の製造方法を示した断面図である。
以上の製造方法により、リードレス表面実装型の半導体装置が完成する。
2 半導体素子搭載領域
3 パイロットホール
4 突起部(上下方向)
5 突起部(左右方向)
6 反り量
7 ダイシングマーク
8 ダイパッド部
9 外部端子部
10 半導体素子
11 ボンディングワイヤ
12 封止樹脂体
13 レジスト層
14 端子等形成領域
15 電鋳
16 個片化された半導体装置
22 外周縁領域
23 半導体素子搭載面
Claims (4)
- 短冊状シートで取り扱われるリードレス表面実装型の半導体装置の製造に用いる半導体素子搭載用基板において、導電性金属板からなるベース基板の半導体素子搭載領域の外周縁領域の各辺に、前記ベース基板をプレス成形して形成された突起部を備え、
前記突起部は、前記ベース基板の前記半導体素子搭載領域の半導体素子搭載面側のみに突出形成されているとともに、
前記突起部は、上下方向の前記突起部と左右方向の前記突起部が交差しない箇所を有するように形成されていることを特徴とするリードレス表面実装型の半導体装置の製造に用いる半導体素子搭載用基板。 - 前記突起部は、前記ベース基板の前記半導体素子搭載領域の外周縁領域にパイロットホールより外側に形成されていることを特徴とする請求項1に記載のリードレス表面実装型の半導体装置の製造に用いる半導体素子搭載用基板。
- 前記突起部は、前記ベース基板の外周と平行に長溝状に形成されていることを特徴とする請求項1または2に記載のリードレス表面実装型の半導体装置の製造に用いる半導体素子搭載用基板。
- 前記突起部は不連続に形成され、配列方向に対して重ならない箇所が設けられていることを特徴とする請求項1から3のいずれかに記載のリードレス表面実装型の半導体装置の製造に用いる半導体素子搭載用基板。
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JP2011146585A JP2011146585A (ja) | 2011-07-28 |
JP5618285B2 true JP5618285B2 (ja) | 2014-11-05 |
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JP6146732B2 (ja) * | 2013-01-18 | 2017-06-14 | Shマテリアル株式会社 | 半導体素子搭載用基板及びその製造方法 |
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JP2007305619A (ja) * | 2006-05-08 | 2007-11-22 | Mitsui High Tec Inc | リードフレーム連設体およびその製造方法 |
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