JP6146732B2 - 半導体素子搭載用基板及びその製造方法 - Google Patents
半導体素子搭載用基板及びその製造方法 Download PDFInfo
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- JP6146732B2 JP6146732B2 JP2013007577A JP2013007577A JP6146732B2 JP 6146732 B2 JP6146732 B2 JP 6146732B2 JP 2013007577 A JP2013007577 A JP 2013007577A JP 2013007577 A JP2013007577 A JP 2013007577A JP 6146732 B2 JP6146732 B2 JP 6146732B2
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- 239000004065 semiconductor Substances 0.000 title claims description 106
- 239000000758 substrate Substances 0.000 title claims description 87
- 238000004519 manufacturing process Methods 0.000 title claims description 26
- 238000000034 method Methods 0.000 claims description 19
- 238000007373 indentation Methods 0.000 claims description 15
- 239000002184 metal Substances 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
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- 238000000465 moulding Methods 0.000 claims description 4
- 239000002585 base Substances 0.000 description 43
- 229920005989 resin Polymers 0.000 description 19
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- 238000007789 sealing Methods 0.000 description 17
- 238000005323 electroforming Methods 0.000 description 14
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- 239000000243 solution Substances 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 229910000990 Ni alloy Inorganic materials 0.000 description 2
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- 239000002994 raw material Substances 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
図1は、従来のリードレス表面実装型の半導体装置の製造方法を示す断面図である。先ず、図1(A)に示すように、厚さが0.1〜0.5mmのステンレスや銅等の導電性金属板から成るベース基板1に、プレスやエッチング等によってパイロットホールを形成する(パイロットホールは図示せず)。このパイロットホールは、この後の工程において位置合わせ基準として使用される。
そして、この凹状圧痕部12は、長溝状の溝の底部がベース基板1の反り湾曲面外側(弧の外側)のみに反り方向に直交する方向に伸びるように反り方向のみに沿って複数個形成されている。
2 レジスト層
3 外部端子部
4 ダイパッド部
5 ボンディングワイヤ
6 半導体素子
7 封止樹脂
8 パイロットホール
9 外周縁領域
10 半導体素子搭載用基板
11 反り量
12 凹状圧痕部
13 V型パンチ
Claims (2)
- 導電性金属板からなるベース基板の半導体素子搭載領域に多数組のダイパッド部と外部端子部が電鋳形成されていて、短冊状シートで取り扱われリードレス表面実装型の半導体装置の製造に用いられる半導体素子搭載用基板であって、前記ベース基板の半導体素子搭載面側の半導体素子搭載領域の外周縁領域のみに前記ベース基板をプレス成形することにより反り方向のみに沿って複数個形成された凹状圧痕部を備え、個々の前記凹状圧痕部は縦断面V形の長溝状で溝の底部が反り方向に直交する方向のみに伸び、半導体素子搭載面に対向する面側は平面であることを特徴とする半導体素子搭載用基板。
- 短冊状シートで取り扱われリードレス表面実装型の半導体装置の製造に用いられる半導体素子搭載用基板の製造方法において、導電性金属板からなるベース基板の半導体素子搭載領域に多数組のダイパッド部と外部端子部を電鋳形成した後に、前記ベース基板の半導体素子搭載領域の外周縁領域のみに、V型パンチを用いてプレス成形することにより、縦断面V形の長溝状で溝の底部が反り方向に直交する方向のみに伸びる凹状圧痕部を反り方向のみに沿って複数個形成することを特徴とする半導体素子搭載用基板の製造方法。
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JP2014138170A JP2014138170A (ja) | 2014-07-28 |
JP6146732B2 true JP6146732B2 (ja) | 2017-06-14 |
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Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04337659A (ja) * | 1991-05-15 | 1992-11-25 | Mitsubishi Electric Corp | リードフレーム |
JPH0864749A (ja) * | 1994-08-25 | 1996-03-08 | Hitachi Cable Ltd | リードフレーム |
JP3115238B2 (ja) * | 1996-09-09 | 2000-12-04 | 株式会社東芝 | 窒化けい素回路基板 |
JP3355288B2 (ja) * | 1997-05-26 | 2002-12-09 | 山一電機株式会社 | 半導体搭載用配線板 |
NL1011929C2 (nl) * | 1999-04-29 | 2000-10-31 | 3P Licensing Bv | Werkwijze voor het inkapselen van elektronische componenten, in het bijzonder geintegreerde schakelingen. |
JP2002016181A (ja) * | 2000-04-25 | 2002-01-18 | Torex Semiconductor Ltd | 半導体装置、その製造方法、及び電着フレーム |
JP4678941B2 (ja) * | 2000-12-14 | 2011-04-27 | 日本インター株式会社 | 複合半導体装置 |
JP2006278914A (ja) * | 2005-03-30 | 2006-10-12 | Aoi Electronics Co Ltd | 半導体装置の製造方法、半導体装置および樹脂封止体 |
JP5011587B2 (ja) * | 2006-03-31 | 2012-08-29 | Dowaメタルテック株式会社 | 放熱板の製造法 |
JP2007305619A (ja) * | 2006-05-08 | 2007-11-22 | Mitsui High Tec Inc | リードフレーム連設体およびその製造方法 |
JP5618285B2 (ja) * | 2010-01-15 | 2014-11-05 | Shマテリアル株式会社 | リードレス表面実装型の半導体装置の製造に用いる半導体素子搭載用基板 |
JP5762078B2 (ja) * | 2011-03-28 | 2015-08-12 | 新光電気工業株式会社 | リードフレーム |
JP5565819B2 (ja) * | 2012-09-04 | 2014-08-06 | Shマテリアル株式会社 | 半導体装置用基板及び半導体装置 |
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