JP2014138170A - 半導体素子搭載用基板及びその製造方法 - Google Patents
半導体素子搭載用基板及びその製造方法 Download PDFInfo
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- JP2014138170A JP2014138170A JP2013007577A JP2013007577A JP2014138170A JP 2014138170 A JP2014138170 A JP 2014138170A JP 2013007577 A JP2013007577 A JP 2013007577A JP 2013007577 A JP2013007577 A JP 2013007577A JP 2014138170 A JP2014138170 A JP 2014138170A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 97
- 239000000758 substrate Substances 0.000 title claims abstract description 94
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 238000007373 indentation Methods 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052751 metal Inorganic materials 0.000 claims abstract description 12
- 230000002093 peripheral effect Effects 0.000 claims abstract description 9
- 238000000465 moulding Methods 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 21
- 239000002994 raw material Substances 0.000 abstract description 3
- 239000002585 base Substances 0.000 description 41
- 229920005989 resin Polymers 0.000 description 19
- 239000011347 resin Substances 0.000 description 19
- 238000007789 sealing Methods 0.000 description 17
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- 238000007796 conventional method Methods 0.000 description 3
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- 239000000243 solution Substances 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
【解決手段】導電性金属板からなるベース基板1の半導体素子搭載領域の外周縁領域9に、ベース基板1をプレス成形することにより形成された凹状圧痕部12を備える。
【選択図】図4
Description
図1は、従来のリードレス表面実装型の半導体装置の製造方法を示す断面図である。先ず、図1(A)に示すように、厚さが0.1〜0.5mmのステンレスや銅等の導電性金属板から成るベース基板1に、プレスやエッチング等によってパイロットホールを形成する(パイロットホールは図示せず)。このパイロットホールは、この後の工程において位置合わせ基準として使用される。
そして、この凹状圧痕部12は、ベース基板1の反り湾曲面外側(弧の外側)のみに反り方向に直交する方向に伸びるように形成されている。
2 レジスト層
3 外部端子部
4 ダイパッド部
5 ボンディングワイヤ
6 半導体素子
7 封止樹脂
8 パイロットホール
9 外周縁領域
10 半導体素子搭載用基板
11 反り量
12 凹状圧痕部
13 V型パンチ
Claims (2)
- 短冊状シートで取り扱われる半導体素子搭載用基板において、導電性金属板からなるベース基板の半導体素子搭載領域の外周縁領域に、前記ベース基板をプレス成形することにより形成された凹状圧痕部を備えたことを特徴とする半導体素子搭載用基板。
- 短冊状シートで取り扱われる半導体素子搭載用基板の製造方法において、導電性金属板からなるベース基板の半導体素子搭載領域の外周縁領域に、反り方向に直交する方向に伸びる凹状圧痕部を、V型パンチを用いてプレス成形することにより形成したことを特徴とする半導体素子搭載用基板の製造方法。
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JP6146732B2 JP6146732B2 (ja) | 2017-06-14 |
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Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04337659A (ja) * | 1991-05-15 | 1992-11-25 | Mitsubishi Electric Corp | リードフレーム |
JPH0864749A (ja) * | 1994-08-25 | 1996-03-08 | Hitachi Cable Ltd | リードフレーム |
JPH1084059A (ja) * | 1996-09-09 | 1998-03-31 | Toshiba Corp | 窒化けい素回路基板 |
JPH10326848A (ja) * | 1997-05-26 | 1998-12-08 | Yamaichi Electron Co Ltd | 半導体搭載用配線板 |
JP2002016181A (ja) * | 2000-04-25 | 2002-01-18 | Torex Semiconductor Ltd | 半導体装置、その製造方法、及び電着フレーム |
US20020064926A1 (en) * | 1999-04-29 | 2002-05-30 | "3P" Licensing B.V. | Method for manufacturing encapsulated electronic components, particularly integrated circuits |
JP2002184914A (ja) * | 2000-12-14 | 2002-06-28 | Nippon Inter Electronics Corp | 複合半導体装置 |
JP2006278914A (ja) * | 2005-03-30 | 2006-10-12 | Aoi Electronics Co Ltd | 半導体装置の製造方法、半導体装置および樹脂封止体 |
JP2007273682A (ja) * | 2006-03-31 | 2007-10-18 | Dowa Holdings Co Ltd | 放熱板およびその製造法 |
JP2007305619A (ja) * | 2006-05-08 | 2007-11-22 | Mitsui High Tec Inc | リードフレーム連設体およびその製造方法 |
JP2011146585A (ja) * | 2010-01-15 | 2011-07-28 | Sumitomo Metal Mining Co Ltd | 半導体素子搭載用基板及びその製造方法並びにそれを用いた半導体装置の製造方法 |
JP2012204774A (ja) * | 2011-03-28 | 2012-10-22 | Shinko Electric Ind Co Ltd | リードフレーム |
JP2012235172A (ja) * | 2012-09-04 | 2012-11-29 | Sumitomo Metal Mining Co Ltd | 半導体装置用基板及び半導体装置 |
-
2013
- 2013-01-18 JP JP2013007577A patent/JP6146732B2/ja active Active
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04337659A (ja) * | 1991-05-15 | 1992-11-25 | Mitsubishi Electric Corp | リードフレーム |
JPH0864749A (ja) * | 1994-08-25 | 1996-03-08 | Hitachi Cable Ltd | リードフレーム |
JPH1084059A (ja) * | 1996-09-09 | 1998-03-31 | Toshiba Corp | 窒化けい素回路基板 |
JPH10326848A (ja) * | 1997-05-26 | 1998-12-08 | Yamaichi Electron Co Ltd | 半導体搭載用配線板 |
US20020064926A1 (en) * | 1999-04-29 | 2002-05-30 | "3P" Licensing B.V. | Method for manufacturing encapsulated electronic components, particularly integrated circuits |
JP2002016181A (ja) * | 2000-04-25 | 2002-01-18 | Torex Semiconductor Ltd | 半導体装置、その製造方法、及び電着フレーム |
JP2002184914A (ja) * | 2000-12-14 | 2002-06-28 | Nippon Inter Electronics Corp | 複合半導体装置 |
JP2006278914A (ja) * | 2005-03-30 | 2006-10-12 | Aoi Electronics Co Ltd | 半導体装置の製造方法、半導体装置および樹脂封止体 |
JP2007273682A (ja) * | 2006-03-31 | 2007-10-18 | Dowa Holdings Co Ltd | 放熱板およびその製造法 |
JP2007305619A (ja) * | 2006-05-08 | 2007-11-22 | Mitsui High Tec Inc | リードフレーム連設体およびその製造方法 |
JP2011146585A (ja) * | 2010-01-15 | 2011-07-28 | Sumitomo Metal Mining Co Ltd | 半導体素子搭載用基板及びその製造方法並びにそれを用いた半導体装置の製造方法 |
JP2012204774A (ja) * | 2011-03-28 | 2012-10-22 | Shinko Electric Ind Co Ltd | リードフレーム |
JP2012235172A (ja) * | 2012-09-04 | 2012-11-29 | Sumitomo Metal Mining Co Ltd | 半導体装置用基板及び半導体装置 |
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