JP2017501575A5 - - Google Patents

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Publication number
JP2017501575A5
JP2017501575A5 JP2016539908A JP2016539908A JP2017501575A5 JP 2017501575 A5 JP2017501575 A5 JP 2017501575A5 JP 2016539908 A JP2016539908 A JP 2016539908A JP 2016539908 A JP2016539908 A JP 2016539908A JP 2017501575 A5 JP2017501575 A5 JP 2017501575A5
Authority
JP
Japan
Prior art keywords
vias
integrated device
dimension
pad
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016539908A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017501575A (ja
Filing date
Publication date
Priority claimed from US14/251,518 external-priority patent/US9466578B2/en
Application filed filed Critical
Publication of JP2017501575A publication Critical patent/JP2017501575A/ja
Publication of JP2017501575A5 publication Critical patent/JP2017501575A5/ja
Pending legal-status Critical Current

Links

JP2016539908A 2013-12-20 2014-12-17 バンプ領域におけるビアパッドの配置が改良された基板 Pending JP2017501575A (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361919157P 2013-12-20 2013-12-20
US61/919,157 2013-12-20
US14/251,518 US9466578B2 (en) 2013-12-20 2014-04-11 Substrate comprising improved via pad placement in bump area
US14/251,518 2014-04-11
PCT/US2014/070940 WO2015095385A1 (en) 2013-12-20 2014-12-17 Substrate comprising improved via pad placement in bump area

Publications (2)

Publication Number Publication Date
JP2017501575A JP2017501575A (ja) 2017-01-12
JP2017501575A5 true JP2017501575A5 (enExample) 2017-03-16

Family

ID=53400887

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016539908A Pending JP2017501575A (ja) 2013-12-20 2014-12-17 バンプ領域におけるビアパッドの配置が改良された基板

Country Status (5)

Country Link
US (1) US9466578B2 (enExample)
EP (1) EP3084826A1 (enExample)
JP (1) JP2017501575A (enExample)
CN (1) CN105830213B (enExample)
WO (1) WO2015095385A1 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI504320B (zh) * 2014-06-17 2015-10-11 矽品精密工業股份有限公司 線路結構及其製法
US9847244B2 (en) * 2015-07-15 2017-12-19 Chip Solutions, LLC Semiconductor device and method
US10895028B2 (en) 2015-12-14 2021-01-19 Dupont Industrial Biosciences Usa, Llc Nonwoven glucan webs
JP2017130823A (ja) * 2016-01-21 2017-07-27 京セラ株式会社 圧電発振器及びその製造方法
WO2019065656A1 (ja) * 2017-09-29 2019-04-04 大日本印刷株式会社 貫通電極基板及び貫通電極基板を用いた半導体装置
US10510634B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
CN117115869B (zh) * 2023-08-23 2025-02-07 汇科(新加坡)控股私人有限公司 声学层的制备方法、超声波芯片及超声波指纹模组

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3345541B2 (ja) * 1996-01-16 2002-11-18 株式会社日立製作所 半導体装置及びその製造方法
DE69725689T2 (de) 1996-12-26 2004-04-29 Matsushita Electric Industrial Co., Ltd., Kadoma Gedruckte Leiterplatte und elektronische Bauteile
JP3386977B2 (ja) 1997-06-05 2003-03-17 新光電気工業株式会社 多層回路基板
JP3466443B2 (ja) * 1997-11-19 2003-11-10 新光電気工業株式会社 多層回路基板
US6303400B1 (en) 1999-09-23 2001-10-16 International Business Machines Corporation Temporary attach article and method for temporary attach of devices to a substrate
US6940176B2 (en) 2002-05-21 2005-09-06 United Microelectronics Corp. Solder pads for improving reliability of a package
WO2004047167A1 (ja) 2002-11-21 2004-06-03 Nec Corporation 半導体装置、配線基板および配線基板製造方法
TW581323U (en) 2003-02-07 2004-03-21 Via Tech Inc Vertical routing structure
JP3986989B2 (ja) * 2003-03-27 2007-10-03 松下電器産業株式会社 半導体装置
US7939941B2 (en) 2007-06-27 2011-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Formation of through via before contact processing
WO2009048154A1 (ja) 2007-10-12 2009-04-16 Nec Corporation 半導体装置及びその設計方法
JP2009135147A (ja) * 2007-11-28 2009-06-18 Shinko Electric Ind Co Ltd 配線基板及び電子素子の接続構造及び電子装置
JP2009260098A (ja) 2008-04-18 2009-11-05 Shinko Electric Ind Co Ltd 配線基板及び半導体装置
US8227295B2 (en) 2008-10-16 2012-07-24 Texas Instruments Incorporated IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV
US8344503B2 (en) * 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
TWI420643B (zh) 2008-12-16 2013-12-21 力成科技股份有限公司 具有矽穿孔之晶片結構、形成方法以及使用該晶片結構之堆疊構造
US8791549B2 (en) * 2009-09-22 2014-07-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer backside interconnect structure connected to TSVs
JP2011222901A (ja) * 2010-04-14 2011-11-04 Renesas Electronics Corp 半導体装置
WO2012061304A1 (en) 2010-11-02 2012-05-10 Georgia Tech Research Corporation Ultra-thin interposer assemblies with through vias
GB2485830A (en) * 2010-11-26 2012-05-30 Cambridge Silicon Radio Ltd Stacked multi-chip package using encapsulated electroplated pillar conductors; also able to include MEMS elements
US8653658B2 (en) * 2011-11-30 2014-02-18 Taiwan Semiconductor Manufacturing Company, Ltd. Planarized bumps for underfill control
KR101916225B1 (ko) * 2012-04-09 2018-11-07 삼성전자 주식회사 Ｔｓｖ를 구비한 반도체 칩 및 그 반도체 칩 제조방법

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