JP2013543272A5 - - Google Patents
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- Publication number
- JP2013543272A5 JP2013543272A5 JP2013536926A JP2013536926A JP2013543272A5 JP 2013543272 A5 JP2013543272 A5 JP 2013543272A5 JP 2013536926 A JP2013536926 A JP 2013536926A JP 2013536926 A JP2013536926 A JP 2013536926A JP 2013543272 A5 JP2013543272 A5 JP 2013543272A5
- Authority
- JP
- Japan
- Prior art keywords
- dielectric
- vias
- crack arrest
- pad
- rdl
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007935 neutral effect Effects 0.000 claims 6
- 239000002184 metal Substances 0.000 claims 4
- 229910052751 metal Inorganic materials 0.000 claims 4
- 238000001465 metallisation Methods 0.000 claims 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims 2
- 238000000034 method Methods 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 1
- 239000004642 Polyimide Substances 0.000 claims 1
- 229910052802 copper Inorganic materials 0.000 claims 1
- 239000010949 copper Substances 0.000 claims 1
- 229920001721 polyimide Polymers 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/917,144 US8304867B2 (en) | 2010-11-01 | 2010-11-01 | Crack arrest vias for IC devices |
| US12/917,144 | 2010-11-01 | ||
| PCT/US2011/058779 WO2012061381A2 (en) | 2010-11-01 | 2011-11-01 | Crack arrest vias for ic devices |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2013543272A JP2013543272A (ja) | 2013-11-28 |
| JP2013543272A5 true JP2013543272A5 (enExample) | 2014-12-04 |
| JP6008431B2 JP6008431B2 (ja) | 2016-10-19 |
Family
ID=45995781
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2013536926A Active JP6008431B2 (ja) | 2010-11-01 | 2011-11-01 | Ｉｃデバイスのクラックアレストビア |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8304867B2 (enExample) |
| JP (1) | JP6008431B2 (enExample) |
| CN (1) | CN103222050B (enExample) |
| WO (1) | WO2012061381A2 (enExample) |
Families Citing this family (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8569886B2 (en) | 2011-11-22 | 2013-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of under bump metallization in packaging semiconductor devices |
| US9412689B2 (en) * | 2012-01-24 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packaging structure and method |
| US10141202B2 (en) | 2013-05-20 | 2018-11-27 | Qualcomm Incorporated | Semiconductor device comprising mold for top side and sidewall protection |
| US9048149B2 (en) * | 2013-07-12 | 2015-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-alignment structure for wafer level chip scale package |
| JP6253439B2 (ja) * | 2014-02-17 | 2017-12-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| KR102109569B1 (ko) | 2015-12-08 | 2020-05-12 | 삼성전자주식회사 | 전자부품 패키지 및 이를 포함하는 전자기기 |
| CN106898589B (zh) | 2015-12-18 | 2020-03-17 | 联华电子股份有限公司 | 集成电路 |
| JP6672820B2 (ja) * | 2016-01-18 | 2020-03-25 | 株式会社村田製作所 | 電子部品 |
| CN105575935A (zh) * | 2016-02-25 | 2016-05-11 | 中国电子科技集团公司第十三研究所 | Cmos驱动器晶圆级封装及其制作方法 |
| US10818627B2 (en) * | 2017-08-29 | 2020-10-27 | Advanced Semiconductor Engineering, Inc. | Electronic component including a conductive pillar and method of manufacturing the same |
| KR102028715B1 (ko) | 2017-12-19 | 2019-10-07 | 삼성전자주식회사 | 반도체 패키지 |
| US12125811B2 (en) | 2018-06-15 | 2024-10-22 | Texas Instruments Incorporated | Semiconductor structure and method for wafer scale chip package |
| KR102073295B1 (ko) | 2018-06-22 | 2020-02-04 | 삼성전자주식회사 | 반도체 패키지 |
| US11063146B2 (en) | 2019-01-10 | 2021-07-13 | Texas Instruments Incorporated | Back-to-back power field-effect transistors with associated current sensors |
| US11600590B2 (en) * | 2019-03-22 | 2023-03-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package |
| US10825789B1 (en) | 2019-08-26 | 2020-11-03 | Nxp B.V. | Underbump metallization dimension variation with improved reliability |
| CN114651322A (zh) * | 2019-11-12 | 2022-06-21 | 华为技术有限公司 | 芯片堆叠封装结构、电子设备 |
| US20210210462A1 (en) * | 2020-01-06 | 2021-07-08 | Texas Instruments Incorporated | Chip scale package with redistribution layer interrupts |
| KR102815754B1 (ko) * | 2020-10-27 | 2025-06-05 | 삼성전자주식회사 | 반도체 패키지 |
| US11308257B1 (en) * | 2020-12-15 | 2022-04-19 | International Business Machines Corporation | Stacked via rivets in chip hotspots |
| US11862576B2 (en) * | 2021-10-28 | 2024-01-02 | Texas Instruments Incorporated | IC having electrically isolated warpage prevention structures |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6462414B1 (en) * | 1999-03-05 | 2002-10-08 | Altera Corporation | Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad |
| KR100306842B1 (ko) | 1999-09-30 | 2001-11-02 | 윤종용 | 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법 |
| JP3989152B2 (ja) * | 2000-02-08 | 2007-10-10 | 株式会社リコー | 半導体装置パッケージ |
| JP2003243569A (ja) * | 2002-02-18 | 2003-08-29 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
| JP3863161B2 (ja) * | 2004-01-20 | 2006-12-27 | 松下電器産業株式会社 | 半導体装置 |
| TWI268564B (en) * | 2005-04-11 | 2006-12-11 | Siliconware Precision Industries Co Ltd | Semiconductor device and fabrication method thereof |
| KR100804392B1 (ko) | 2005-12-02 | 2008-02-15 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
| KR100790527B1 (ko) | 2006-07-27 | 2008-01-02 | 주식회사 네패스 | 웨이퍼레벨 패키지 및 그 제조 방법 |
| US20080169539A1 (en) * | 2007-01-12 | 2008-07-17 | Silicon Storage Tech., Inc. | Under bump metallurgy structure of a package and method of making same |
| JP2009010260A (ja) * | 2007-06-29 | 2009-01-15 | Fujikura Ltd | 半導体装置 |
| US20090278263A1 (en) | 2008-05-09 | 2009-11-12 | Texas Instruments Incorporated | Reliability wcsp layouts |
| CN101587873A (zh) * | 2008-05-21 | 2009-11-25 | 福葆电子股份有限公司 | 降低应力的介电层结构及其制造方法 |
| US8076786B2 (en) * | 2008-07-11 | 2011-12-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for packaging a semiconductor package |
| JP2010092930A (ja) * | 2008-10-03 | 2010-04-22 | Fujikura Ltd | 半導体装置およびその製造方法 |
| KR20100093357A (ko) | 2009-02-16 | 2010-08-25 | 삼성전자주식회사 | 웨이퍼 레벨 칩스케일 패키지 |
| US8084871B2 (en) * | 2009-11-10 | 2011-12-27 | Maxim Integrated Products, Inc. | Redistribution layer enhancement to improve reliability of wafer level packaging |
-
2010
- 2010-11-01 US US12/917,144 patent/US8304867B2/en active Active
-
2011
- 2011-11-01 CN CN201180056162.1A patent/CN103222050B/zh active Active
- 2011-11-01 JP JP2013536926A patent/JP6008431B2/ja active Active
- 2011-11-01 WO PCT/US2011/058779 patent/WO2012061381A2/en not_active Ceased
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