JP6008431B2 - Icデバイスのクラックアレストビア - Google Patents
Icデバイスのクラックアレストビア Download PDFInfo
- Publication number
- JP6008431B2 JP6008431B2 JP2013536926A JP2013536926A JP6008431B2 JP 6008431 B2 JP6008431 B2 JP 6008431B2 JP 2013536926 A JP2013536926 A JP 2013536926A JP 2013536926 A JP2013536926 A JP 2013536926A JP 6008431 B2 JP6008431 B2 JP 6008431B2
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- Prior art keywords
- dielectric
- crack arrest
- die
- rdl
- vias
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Description
Claims (9)
- 集積回路(IC)デバイスであって、
複数の入力/出力(I/O)ノードと、前記複数のI/Oノードに結合される複数のダイパッドとを含む能動回路要素を含む上面を有する基板と、
前記複数のダイパッドの上の第1の誘電体ビアを含む第1の誘電体層と、
前記第1の誘電体ビアの上の前記複数のダイパッドに結合される複数のRDL捕捉パッドを含むリダイレクト層(RDL)と、
前記複数のRDL捕捉パッドの上の第2の誘電体ビアを含む第2の誘電体層であって、前記第2の誘電体ビアの少なくとも1つがクラックアレストビアであり、前記クラックアレストビアが、前記ICデバイスのニュートラル応力ポイントから離れて面する頂点を含むビア形状を有し、前記頂点が、前記ニュートラル応力ポイントから前記クラックアレストビアへのラインに沿って前記ラインからプラスマイナス30度の範囲で面するように方向付けられる、前記第2の誘電体層と、
前記第2の誘電体ビアの上の前記複数のRDL捕捉パッドに結合されるアンダーバンプメタライゼーション(UBM)パッドと、
前記UBMパッド上の金属ボンディングコネクタと、
を含む、ICデバイス。 - 請求項1に記載のICデバイスであって、
前記頂点が、前記ラインからプラスマイナス15度の範囲で面するように方向付けられる、ICデバイス。 - 請求項1に記載のICデバイスであって、
前記クラックアレストビアのための前記ビア形状が曲線的コーナーを含む三角形である、ICデバイス。 - 請求項1に記載のICデバイスであって、
前記少なくとも一つのクラックアレストビアが、前記ICデバイスの最外周ロー及びコラムに沿った前記第2の誘電体ビアの全てに対し提供される複数のクラックアレストビアを含む、ICデバイス。 - 請求項1に記載のICデバイスであって、
前記金属ボンディングコネクタがはんだボールを含む、ICデバイス。 - 請求項1に記載のICデバイスであって、
前記第1の誘電体層と前記第2の誘電体層とがいずれも、ポリイミド又はベンゾシクロブテン(BCB)を含み、前記RDLが銅を含む、ICデバイス。 - 請求項1に記載のICデバイスであって、
前記ICデバイスがウエハチップスケールパッケージ(WCSP)を含む、ICデバイス。 - 集積回路(IC)デバイスであって、
複数の入力/出力(I/O)ノードと、前記複数のI/Oノードに結合される複数のダイパッドとを含む能動回路要素を含む上面を有する基板と、
前記複数のダイパッドの上の第1の誘電体ビアを含む第1の誘電体層と、
前記第1の誘電体ビアの上の前記複数のダイパッドに結合される複数のRDL捕捉パッドを含むリダイレクト層(RDL)と、
前記複数のRDL捕捉パッドの上の第2の誘電体ビアを含む第2の誘電体層であって、前記第2の誘電体ビアの少なくとも1つがクラックアレストビアであり、前記クラックアレストビアが、前記ICデバイスのニュートラル応力ポイントから離れて面する頂点を含むビア形状を有し、前記頂点が、前記ニュートラル応力ポイントから前記クラックアレストビアへのラインに沿って前記ラインからプラスマイナス15度の範囲で面するように方向付けられる、前記第2の誘電体層と、
前記第2の誘電体ビアの上の前記複数のRDL捕捉パッドに結合されるアンダーバンプメタライゼーション(UBM)パッドと、
前記UBMパッド上の金属ボンディングコネクタと、
を含み、
前記クラックアレストビアのための前記ビア形状が、曲線的コーナーを含む三角形であり、
前記少なくとも一つのクラックアレストビアが、前記ICデバイスの最外周ロー及びコラムに沿った前記第2の誘電体ビアの全てに対し提供される複数のクラックアレストビアを含む、ICデバイス。 - 集積回路(IC)デバイスを形成する方法であって、
複数のICダイを含む頂部半導体表面を有するウエハを提供することであって、前記ICダイが、複数の入力/出力(I/O)ノードと、前記複数のI/Oノードに結合される複数のダイパッドとを含む能動回路要素を含む、前記ウエハを提供することと、
前記複数のダイパッドの上の第1の誘電体ビアを含む第1の誘電体層を形成することと、
前記複数の第1の誘電体ビアの上の前記複数のダイパッドに結合される前記第1の誘電体層上に複数のRDL捕捉パッドを含むリダイレクト層(RDL)を形成することと、
前記複数のRDL捕捉パッドの上の第2の誘電体ビアを含む第2の誘電体層を形成することであって、前記第2の誘電体ビアの少なくとも1つがクラックアレストビアであり、前記クラックアレストビアが、前記ICダイのニュートラル応力ポイントから離れて面する頂点を含むビア形状を有し、前記頂点が、前記ニュートラル応力ポイントから前記クラックアレストビアへのラインに沿って前記ラインからプラスマイナス30度の範囲に面するように方向付けられる、前記第2の誘電体層を形成することと、
前記複数のRDL捕捉パッドの各々の上の前記第2の誘電体ビアの上にアンダーバンプメタライゼーション(UBM)パッドを形成することと、
前記UBMパッド上に金属ボンディングコネクタを形成することと、
を含む、方法。
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US12/917,144 US8304867B2 (en) | 2010-11-01 | 2010-11-01 | Crack arrest vias for IC devices |
PCT/US2011/058779 WO2012061381A2 (en) | 2010-11-01 | 2011-11-01 | Crack arrest vias for ic devices |
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Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8569886B2 (en) | 2011-11-22 | 2013-10-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus of under bump metallization in packaging semiconductor devices |
US9412689B2 (en) * | 2012-01-24 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packaging structure and method |
US10141202B2 (en) * | 2013-05-20 | 2018-11-27 | Qualcomm Incorporated | Semiconductor device comprising mold for top side and sidewall protection |
US9048149B2 (en) * | 2013-07-12 | 2015-06-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-alignment structure for wafer level chip scale package |
JP6253439B2 (ja) * | 2014-02-17 | 2017-12-27 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
KR102109569B1 (ko) | 2015-12-08 | 2020-05-12 | 삼성전자주식회사 | 전자부품 패키지 및 이를 포함하는 전자기기 |
CN106898589B (zh) | 2015-12-18 | 2020-03-17 | 联华电子股份有限公司 | 集成电路 |
JP6672820B2 (ja) * | 2016-01-18 | 2020-03-25 | 株式会社村田製作所 | 電子部品 |
CN105575935A (zh) * | 2016-02-25 | 2016-05-11 | 中国电子科技集团公司第十三研究所 | Cmos驱动器晶圆级封装及其制作方法 |
US10818627B2 (en) * | 2017-08-29 | 2020-10-27 | Advanced Semiconductor Engineering, Inc. | Electronic component including a conductive pillar and method of manufacturing the same |
KR102028715B1 (ko) * | 2017-12-19 | 2019-10-07 | 삼성전자주식회사 | 반도체 패키지 |
US20190385962A1 (en) * | 2018-06-15 | 2019-12-19 | Texas Instruments Incorporated | Semiconductor structure and method for wafer scale chip package |
KR102073295B1 (ko) | 2018-06-22 | 2020-02-04 | 삼성전자주식회사 | 반도체 패키지 |
US11063146B2 (en) | 2019-01-10 | 2021-07-13 | Texas Instruments Incorporated | Back-to-back power field-effect transistors with associated current sensors |
US11600590B2 (en) * | 2019-03-22 | 2023-03-07 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package |
US10825789B1 (en) | 2019-08-26 | 2020-11-03 | Nxp B.V. | Underbump metallization dimension variation with improved reliability |
KR20220056309A (ko) * | 2020-10-27 | 2022-05-06 | 삼성전자주식회사 | 반도체 패키지 |
US11308257B1 (en) * | 2020-12-15 | 2022-04-19 | International Business Machines Corporation | Stacked via rivets in chip hotspots |
US11862576B2 (en) * | 2021-10-28 | 2024-01-02 | Texas Instruments Incorporated | IC having electrically isolated warpage prevention structures |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6462414B1 (en) * | 1999-03-05 | 2002-10-08 | Altera Corporation | Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad |
KR100306842B1 (ko) | 1999-09-30 | 2001-11-02 | 윤종용 | 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법 |
JP3989152B2 (ja) * | 2000-02-08 | 2007-10-10 | 株式会社リコー | 半導体装置パッケージ |
JP2003243569A (ja) * | 2002-02-18 | 2003-08-29 | Matsushita Electric Ind Co Ltd | 半導体装置およびその製造方法 |
JP3863161B2 (ja) * | 2004-01-20 | 2006-12-27 | 松下電器産業株式会社 | 半導体装置 |
TWI268564B (en) * | 2005-04-11 | 2006-12-11 | Siliconware Precision Industries Co Ltd | Semiconductor device and fabrication method thereof |
KR100804392B1 (ko) | 2005-12-02 | 2008-02-15 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
KR100790527B1 (ko) | 2006-07-27 | 2008-01-02 | 주식회사 네패스 | 웨이퍼레벨 패키지 및 그 제조 방법 |
US20080169539A1 (en) * | 2007-01-12 | 2008-07-17 | Silicon Storage Tech., Inc. | Under bump metallurgy structure of a package and method of making same |
JP2009010260A (ja) * | 2007-06-29 | 2009-01-15 | Fujikura Ltd | 半導体装置 |
US20090278263A1 (en) | 2008-05-09 | 2009-11-12 | Texas Instruments Incorporated | Reliability wcsp layouts |
CN101587873A (zh) * | 2008-05-21 | 2009-11-25 | 福葆电子股份有限公司 | 降低应力的介电层结构及其制造方法 |
US8076786B2 (en) * | 2008-07-11 | 2011-12-13 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for packaging a semiconductor package |
JP2010092930A (ja) * | 2008-10-03 | 2010-04-22 | Fujikura Ltd | 半導体装置およびその製造方法 |
KR20100093357A (ko) | 2009-02-16 | 2010-08-25 | 삼성전자주식회사 | 웨이퍼 레벨 칩스케일 패키지 |
US8084871B2 (en) * | 2009-11-10 | 2011-12-27 | Maxim Integrated Products, Inc. | Redistribution layer enhancement to improve reliability of wafer level packaging |
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