CN103222050B - 用于ic器件的止裂通孔 - Google Patents

用于ic器件的止裂通孔 Download PDF

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Publication number
CN103222050B
CN103222050B CN201180056162.1A CN201180056162A CN103222050B CN 103222050 B CN103222050 B CN 103222050B CN 201180056162 A CN201180056162 A CN 201180056162A CN 103222050 B CN103222050 B CN 103222050B
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hole
dielectric
rdl
pad
crack arrest
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CN103222050A (zh
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R·F·麦卡锡
S·C·贝汀菲儿
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

一种集成电路（IC）器件（300），其包括具有顶表面（304）的衬底（305），顶表面（304）包括有源电路（309）和多个管芯焊盘（302），有源电路（309）包括多个I/O节点（308），多个管芯焊盘（302）耦合到该多个I/O节点。包括第一介电通孔（312）的第一介电层（306）在多个管芯焊盘上方。包括多个RDL捕获焊盘（318）的重定向层（RDL）（314）经由第一介电通孔耦合到多个管芯焊盘。包括第二介电通孔（322）的第二介电层（320）在多个RDL捕获焊盘上方。第二介电通孔中的至少一个是具有包括一顶端的通孔形状的止裂通孔，该顶端背向IC管芯的中性应力点并沿从该中性应力点到止裂通孔的线条取向，从而面向线条，与线条的角度在±30度的范围内。凸点下金属化（UBM）焊盘（324）经由第二介电通孔耦合到多个RDL捕获焊盘，并且金属键合连接体（326）在该UBM焊盘上。

Description

用于IC器件的止裂通孔
技术领域
公开的实施例涉及集成电路（IC），并且更特别涉及芯片级封装。
背景技术
具有增加的功能性的更小、更便携的电子产品的需求已在许多市场和应用中加速增长。为了提供这些产品，设计师已转向尺寸减小的封装方法，例如芯片级封装（CSP）。CSP的一种特定实现，即晶圆CSP（WCSP），允许封装尺寸被减小到管芯自身的尺寸，并且消除了较大CSP中常见的较大插入层（interposerlayer）的需要。
WCSP通过使用IC管芯自身作为WCSP衬底，消除了附连到封装衬底的常规封装步骤，例如管芯键合、引线键合以及管芯级倒装芯片附连工艺。与附连到较大占位面积（footprint）封装衬底（例如PCB衬底）的相同IC管芯相比，使用管芯自身作为WCSP衬底极大地减小了到IC管芯自身的占位面积。
WCSP可以被实施为直接凸点（direct-bump）WCSP或重定向层（RDL）WSCP，与直接凸点WCSP不同的是，重定向层（RDL）WSCP添加用作重布线层的RDL，从而能够将外部输入/输出（I/O）端子重定位在期望的位置。在通常的RDLWCSP生产流程中，在常规的后段制程（BEOL）晶圆厂加工完成之后，除了在管芯焊盘上方的钝化开口之外，WCSP管芯通常还包括在BEOL金属堆叠上方的管芯焊盘（也称为键合焊盘）和介电钝化层。淀积第一WCSP电介质（例如聚酰亚胺）。光刻/刻蚀在管芯焊盘上方第一WCSP电介质中形成第一介电通孔，之后淀积和图形化包括多条RDL迹线的RDL金属，该RDL迹线接触管芯焊盘并且从这里横向延伸到RDL捕获焊盘（capturepad）。接着淀积第二WCSP电介质（例如聚酰亚胺），并且形成第二介电通孔，第二介电通孔到达在管芯焊盘的位置侧面的RDL捕获焊盘位置中的RDL。第一和第二介电通孔的截面形状都是常规圆形的，或在一些情况下是正方形的。
通常称为“球形焊盘”或“凸点焊盘”的凸点下金属化（UBM）焊盘在第二介电通孔上方形成，并且耦合到RDL捕获焊盘且通常由该RDL捕获焊盘包围，之后在UBM焊盘上形成金属（例如焊料）球、立柱或其他键合连接体。每个键合连接体（例如焊球）为WCSP管芯提供了重定位的外部I/O连接。接着，WCSP晶圆被分割（singulate），从而形成多个分割的WCSP管芯，这些WCSP管芯通常用在板件面积宝贵的便携装置的板件上。
WSCP器件的一个挑战是可靠性。通常，板件级可靠性（BLR）测试包括温度循环（TC）、下落和弯曲测试。对于BLR-TC，WCSP通常是安装到有机印刷电路板上并且经受TC，并且评估RDL和焊球的特性，以及在其间使用的任何粘合层或扩散势垒层的特性。随着WCSP管芯尺寸增加，已经知道，在BLR-TC测试期间以加速方式可以证明的可靠性降低。通常通过实现对WCSP工艺和材料的改变（例如替换电介质）来解决WCSP管芯的BLR-TC性能，这可以稍微提高BLR-TC性能。
发明内容
发明人认识到，由于到中性应力点（NSP）距离的相关问题，具有包含由通孔耦合到金属焊盘的键合导体的I/O的常规IC器件可能不能在BLR-TC测试中或更一般地在现场使用期间表现良好。到NSP距离的问题会导致管芯上的外围I/O与非外围I/O相比，在现场使用或BLP-TC测试期间倾向于以较高速率失效。发明人已认识到，WCSP管芯的这种失效是由于在焊球或其他金属键合连接体下面的第二层介电通孔开口处的RDL焊盘中的破裂引起的。在电路工作期间，外围I/O的电阻随着该破裂位置在该通孔开口周围传播而增加，并且会最终导致由于开路而引起的电气失效。
尽管对WCSP工艺和材料的改变可以稍微改善可靠性，包括在BLR-TC执行期间的可靠性，但需要进一步改善可靠性以减小失效率。与常规解决方案相比，所公开的实施例尝试涉及修改可以在不影响工艺或材料的情况下实现的CSP设计特征，已发现，这显著进一步改善了WCSP可靠性。所公开的IC器件包含第一介电层、重定向层（RDL）和第二介电层，该第一介电层包括在多个管芯焊盘上方的第一介电通孔，该RDL包括经由第一介电通孔耦合到多个管芯焊盘的多个RDL捕获焊盘，该第二介电层包括在多个RDL捕获焊盘上方的第二介电通孔。至少一个第二介电通孔是在此称为的“止裂通孔（crackarrestvia）”。止裂通孔具有包括一顶端的通孔形状，该顶端背向IC管芯上的NSP并且沿从NSP到止裂通孔的线条取向，从而面向（指向）该线条，与该线条的角度在±30度的范围内，并且在一个实施例中，与该线条的角度在±15度的范围内。
已发现，由所公开的实施例提供的BLR-TC改善包括（i）由于在RDL和UBM之间具有更多的第二介电材料，因此减小了第二电介质裂纹/裂缝的发生率/密度和尺寸，这是因为与常规圆形或正方形通孔相比，止裂通孔形状通过增加键合导体（例如焊球）和RDL焊盘之间的第二电介质的量来降低了总应力分布。另外，BLR-TC改善包括（ii）对于形成的有限数目的第二电介质裂缝，通过将止裂通孔的顶端取向为背向到NSP的线条，这些裂缝被偏离RDL焊盘，这起到了引导这些裂缝横向离开止裂通孔的作用。由发明人获得的应力建模和经验数据都证实了，所公开的止裂通孔通过增加平均失效时间（MTF）而改善了可靠性，并且也改善了BLR性能。
附图说明
图1示出了在示例WCSP器件上的焊盘的示例应力分布。
图2A示出根据公开的实施例的沿WCSP管芯的最外行和最外列具有三角形止裂通孔的示例WCSP管芯部分。
图2B示出根据公开的实施例的示例三角形止裂通孔，该止裂通孔具有与到管芯的NSP的线条背向的顶端。
图3示出根据公开的实施例的具有止裂通孔的示例WCSP管芯的一部分的截面图。
图4示出根据公开的实施例的经验结果，这些结果证明了与常规圆形通孔相比，具有所公开的止裂通孔的WCSP管芯的TC性能得到了BLR改善。
具体实施方式
发明人已发现，加工和材料的改变仅有限地改善WCSP器件可靠性。此外，已经认识到，影响WCSP器件，特别是对于具有大量焊球（例如，>80个）的超过9mm2管芯尺寸的WCSP器件的可靠性的主要原因是WCSP器件和PCB（特别是有机PCB）之间的热膨胀系数（CTE）的差引起的应力。随着温度改变，PCB会相对于WCSP器件膨胀，从而在WCSP管芯中的各层中产生压缩力和张力。特别地，这些力对于WCSP管芯更靠近管芯边缘的部分是增加的，从而增加了这些区域中的应力，尤其是在WSCP管芯的UBM焊盘（凸点焊盘）附近。因此，在WCSP管芯上，随着UBM焊盘到NSP（通常是管芯中心）的距离增加，在UBM焊盘处的应力也增加，发明人已认识到，这会导致在焊球或其他键合导体下面的第二电介质中开始出现电介质裂缝。
在图1中示出了UBM焊盘102（包括焊盘108、110和112）在WCSP管芯100上的示例应力分布图案（pattern）。由于在上面描述的各种力，WCSP管芯100上的每一个UBM焊盘102的物理应力的量会变化。发明人已发现，WCSP管芯100中的应力在本质上一般是径向的，这是由于弯曲量沿WCSP管芯100的边缘增加。因此，随着WCSP管芯100的UBM焊盘102和NSP106（由“X”示出）之间的距离增加，UBM焊盘102上的应力也会增加。然而，应力图案在整个WCSP管芯100上未必是均匀的。例如，在WCSP管芯100的中心区域104中，应力图案可以是最小的。该最小应力通常与最靠近WCSP管芯100的NSP106的UBM焊盘102（即，与NSP的距离较近的UBM焊盘102）关联。
如在此使用的IC管芯的NSP指代应力被最小化或为零的点。通常，NSP106在WCSP管芯100的几何中心处，或接近该几何中心。在一些情况下，根据在管芯上形成的层的数目、类型和图案，NSP106可以偏离WCSP管芯100的几何中心。例如，在功能电路形成有功能电路的高密度区域和低密度区域的情况下，密度的变化（并且因此功能电路层的变化）会导致管芯应力的变化，管芯应力的变化会导致NSP偏离WCSP管芯100的几何中心。在另一示例中，随着WCSP管芯的形状变化，弯曲的局部变化和全局变化也会使WCSP管芯100的NSP偏离其几何中心。
如在此使用，到NSP的距离指代从NSP106到特征的中心的距离。在重叠且对齐的特征的情况下，到NSP的距离对于全部特征是相同的。例如，在一系列同心重叠形状（例如定义通孔和导体的层的一组同心圆或矩形特征）的情况下，每一个特征到NSP的距离是从NSP106到该特征的几何中心进行测量的。然而，在一些情况下，形状可以不是同心的。在这些情况下，每个特征到NSP的距离是从每个特征的几何中心进行测量的。然而，多个相关特征可以形成在一层中并且与单个特征关联。例如，两个或更多个通孔可以用来连接不同层中的两个焊盘。在这些情况下，多个通孔可以被认为包括单个特征，并且因此到NSP的距离可以从通孔的几何中心进行测量。
尽管UBM焊盘102到NSP106的整个距离通常是影响可靠性的主要因素，但其可能不是唯一因素。例如，在通常的管芯中，UBM焊盘108中的应力通常小于UBM焊盘110中的应力。发明人已发现，对于更靠近管芯的拐角形成的UBM焊盘，例如UBM焊盘110，应力通常是进一步增强的，从而导致更大可能性的失效。另外，对于到NSP的距离相同的UBM焊盘，应力也会由于其他效应而进一步增强。例如，如在上面描述的，功能电路密度的变化也会导致径向应力图案的局部变化。在另一示例中，WCSP管芯尺寸和形状的变化也会导致应力的变化。
图2A示出根据公开的实施例的沿其最外行和最外列在第二介电层220中具有三角形止裂通孔250的示例WCSP管芯部分（管芯的四分之一）200。在WCSP管芯部分200上示出的其他通孔是常规圆形通孔240。在WCSP管芯部分200的拐角中示出的止裂通孔250中的特定一个被编号为250’。三角形通孔形状被描绘为等边三角形（即，全部三个侧边具有相同长度）。
在止裂通孔之外的环分别代表UBM焊盘231和在UBM焊盘231下面的RDL焊盘232。也示出了管芯焊盘242。示出了对应于WCSP管芯部分200的管芯中心，并且为了简便，将其假设为管芯上的NSP106。线条211被示为从NSP106到三角形止裂通孔250和250’。
可以看到，这些三角形止裂通孔250和250’被取向为，它们的顶端中被示为251的一个顶端背向NSP106并且沿从NSP106到三角形止裂通孔的线条211进行取向，从而面向线条，或更一般地与该线条的角度在±30度的范围内。已发现，顶端251的这个取向使第二电介质中朝着在止裂通孔250和250’（以及通孔240）中的每一个下面的RDL焊盘232垂直向下传播而形成的数目减少的裂缝横向偏离。此外，这个取向使得顶端251在三角形止裂通孔250的最高应力点处，因为顶端251到NSP106的距离是三角形止裂通孔250和250’的任何边缘部分中最大的。
图2B示出根据公开的实施例的在图2A中示出的WCSP管芯部分200的拐角中的示例三角形止裂通孔250’的放大图，该止裂通孔250’的一个顶端251背向管芯的NSP106并且沿从NSP106到三角形止裂通孔250’的线条对齐，从而面向线条，与线条的角度在±30度的范围内。示出了圆形通孔拐角254。如在此使用，“圆形拐角”被定义为连接三角形通孔的相邻支线的弯曲轮廓，其中该弯曲轮廓对向（subtend）至少30度的中心角。发明人已发现，与由尖顶区域生成的应力相比，圆形拐角通过减少应力集中度进一步减少了裂缝。
由于与常规圆形通孔相比，示例三角形止裂通孔250在RDL和UBM之间具有更多的第二电介质，这也使第二电介质裂纹/裂缝的发生率/密度和尺寸减小。与具有相同半径的常规圆形通孔相比，所公开的三角形止裂通孔250可以将总通孔面积减小约40%，并且因此与常规圆形通孔相比，可以提供多出约高达40%的介电材料，由于在键合导体（例如焊球）和RDL焊盘之间具有更多的第二介电材料，这显著降低了总应力分布。
图3示出根据公开的实施例的具有止裂通孔的示例IC器件300的一部分的截面图。IC器件300包括具有顶表面304的衬底305，该顶表面304包括有源电路309和多个管芯焊盘302，有源电路309包括多个I/O节点，其中示出了节点308，多个管芯焊盘302耦合到该多个I/O节点。第一介电层306包括在管芯焊盘302上方的第一介电通孔312。RDL314包括接触管芯焊盘的焊盘316、RDL迹线（包括RDL迹线318）以及多个RDL捕获焊盘，其中RDL捕获焊盘319被示为通过RDL迹线318经由第一介电通孔312耦合到管芯焊盘302。第二介电层320包括在多个RDL捕获焊盘（包括RDL焊盘319）上方的第二介电通孔322。示出的第二介电通孔322包括公开的止裂通孔，例如在图2A和2B中示出的三角形止裂通孔250或250’。
凸点下金属化（UBM）焊盘324经由第二介电通孔322耦合到多个RDL捕获焊盘（包括RDL捕获焊盘319）。示为焊球的金属键合连接体326在UBM焊盘324上。尽管键合连接体326被示为焊球，但用于所公开的实施例的键合连接体可以包括其他键合连接体，例如立柱（例如铜立柱）、贯穿衬底通孔和钉头（stud）（例如金钉头）。在一个实施例中，第一介电层和第二介电层都包括聚酰亚胺或苯并环丁烯（BCB），并且RDL包括铜。可以在第二介电层320上方形成在图3中示出的覆盖介电膜327。
图4示出根据公开的实施例的经验结果，其证明了与常规圆形通孔相比，具有所公开的止裂通孔的WCSP管芯的TC性能得到了BLR改善。从-40℃到125℃执行TC测试，其中WCSP管芯键合到FR4（有机）衬底。可以看到，与包括常规圆形第二介电通孔的常规WCSP管芯相比，在5%的失效速率（FR）的情况下，所公开的止裂通孔使BLR-TC性能（在有机衬底上的WCSP管芯）得到了177%的改善。
在晶圆半导体衬底上形成的有源电路包括电路元件（其通常可以包括晶体管、二极管、电容器和电阻器）以及将各种电路元件互连的信号线和其他电导体。所公开的实施例可以被集成到多种工艺流程中，从而形成多种器件和相关产品。半导体衬底可以包括在其中的各种元件和/或在其上的层。这些元件和层可以包括势垒层、其他介电层、器件结构、有源元件和无源元件，包括源区、漏区、位线、基极、发射极、集电极、导线、导电通孔等。此外，所公开的实施例可以用在多种半导体器件制造工艺中，包括双极工艺、CMOS工艺、BiCMOS工艺和MEMS工艺。
本公开涉及的本领域技术人员认识到，在本发明的范围内，许多其他实施例和实施例的变化是可能的，并且在不背离本公开的范围的情况下，可以对所描述的实施例进行进一步添加、删除、替换和修改。

Claims (10)

1.一种集成电路器件，即IC器件，其包括：
衬底，所述衬底具有顶表面，所述顶表面包括有源电路和多个管芯焊盘，所述有源电路包括多个I/O节点，所述多个管芯焊盘耦合到所述多个I/O节点；
第一介电层，所述第一介电层包括在所述多个管芯焊盘上方的第一介电通孔；
重定向层，即RDL，所述RDL包括经由所述第一介电通孔耦合到所述多个管芯焊盘的多个RDL捕获焊盘；
第二介电层，所述第二介电层包括在所述多个RDL捕获焊盘上方的第二介电通孔，其中所述第二介电通孔中的至少一个是止裂通孔，所述止裂通孔具有包括一顶端的通孔形状，该顶端背向IC管芯的中性应力点并且沿从所述中性应力点到所述止裂通孔的线条取向，从而面向所述线条，与所述线条的角度在±30度的范围内；
凸点下金属化焊盘，即UBM焊盘，所述UBM焊盘经由所述第二介电通孔耦合到所述多个RDL捕获焊盘，以及
在所述UBM焊盘上的金属键合连接体。
2.根据权利要求1所述的IC器件，其中所述顶端被取向为面向所述线条，与所述线条的角度在±15度的范围内。
3.根据权利要求1所述的IC器件，其中所述止裂通孔的所述通孔形状是包括圆形拐角的三角形。
4.根据权利要求1所述的IC器件，其中所述至少一个止裂通孔包括沿所述IC器件的最外围行和最外围列为所有所述第二介电通孔提供的多个止裂通孔。
5.根据权利要求1所述的IC器件，其中沿所述IC器件的三个最外围行和最外围列为所有所述第二介电通孔提供所述多个止裂通孔，所述IC器件的三个最外围行和最外围列包括所述IC器件的所述最外围行和最外围列。
6.根据权利要求1所述的IC器件，其中所述金属键合连接体包括焊球。
7.根据权利要求1所述的IC器件，其中所述第一介电层和所述第二介电层都包括聚酰亚胺或苯并环丁烯，即BCB，并且所述RDL包括铜。
8.根据权利要求1所述的IC器件，其中所述IC器件包括晶圆芯片级封装，即WCSP。
9.一种集成电路器件，即IC器件，其包括：
衬底，所述衬底具有顶表面，所述顶表面包括有源电路和多个管芯焊盘，所述有源电路包括多个I/O节点，所述多个管芯焊盘耦合到所述多个I/O节点；
第一介电层，所述第一介电层包括在所述多个管芯焊盘上方的第一介电通孔；
重定向层，即RDL，所述RDL包括经由所述第一介电通孔耦合到所述多个管芯焊盘的多个RDL捕获焊盘；
第二介电层，所述第二介电层包括在所述多个RDL捕获焊盘上方的第二介电通孔，其中所述第二介电通孔中的至少一个是止裂通孔，所述止裂通孔具有包括一顶端的通孔形状，该顶端背向IC管芯的中性应力点并且沿从所述中性应力点到所述止裂通孔的线条取向，从而面向所述线条，与所述线条的角度在±15度的范围内；
凸点下金属化焊盘，即UBM焊盘，所述UBM焊盘经由所述第二介电通孔耦合到所述多个RDL捕获焊盘；
在所述UBM焊盘上的金属键合连接体；
其中所述止裂通孔的所述通孔形状是包括圆形拐角的三角形，以及
其中所述至少一个止裂通孔包括沿所述IC器件的最外围行和最外围列为所有所述第二介电通孔提供的多个止裂通孔。
10.一种形成集成电路器件，即IC器件的方法，其包括：
提供具有顶部半导体表面的晶圆，所述顶部半导体表面包括多个IC管芯，所述IC管芯包括有源电路和多个管芯焊盘，所述有源电路包括多个I/O节点，所述多个管芯焊盘耦合到所述多个I/O节点；
形成重定向层，即RDL，所述RDL包括在第一介电层上的多个RDL捕获焊盘，所述多个RDL捕获焊盘经由所述多个第一介电通孔耦合到所述多个管芯焊盘；
形成第二介电层，所述第二介电层包括在所述多个RDL捕获焊盘上方的第二介电通孔，其中所述第二介电通孔中的至少一个是止裂通孔，所述止裂通孔具有包括一顶端的通孔形状，该顶端背向所述IC管芯的中性应力点并且沿从所述中性应力点到所述止裂通孔的线条取向，从而面向所述线条，与所述线条的角度在±30度的范围内；
在所述多个RDL捕获焊盘中的每一个上，所述第二介电通孔上方形成凸点下金属化焊盘，即UBM焊盘，以及
在所述UBM焊盘上形成金属键合连接体。
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Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8569886B2 (en) 2011-11-22 2013-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of under bump metallization in packaging semiconductor devices
US9412689B2 (en) * 2012-01-24 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packaging structure and method
US10141202B2 (en) * 2013-05-20 2018-11-27 Qualcomm Incorporated Semiconductor device comprising mold for top side and sidewall protection
US9048149B2 (en) * 2013-07-12 2015-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Self-alignment structure for wafer level chip scale package
JP6253439B2 (ja) * 2014-02-17 2017-12-27 ルネサスエレクトロニクス株式会社 半導体装置
KR102109569B1 (ko) 2015-12-08 2020-05-12 삼성전자주식회사 전자부품 패키지 및 이를 포함하는 전자기기
CN106898589B (zh) 2015-12-18 2020-03-17 联华电子股份有限公司 集成电路
JP6672820B2 (ja) * 2016-01-18 2020-03-25 株式会社村田製作所 電子部品
CN105575935A (zh) * 2016-02-25 2016-05-11 中国电子科技集团公司第十三研究所 Cmos驱动器晶圆级封装及其制作方法
US10818627B2 (en) * 2017-08-29 2020-10-27 Advanced Semiconductor Engineering, Inc. Electronic component including a conductive pillar and method of manufacturing the same
KR102028715B1 (ko) * 2017-12-19 2019-10-07 삼성전자주식회사 반도체 패키지
US12125811B2 (en) * 2018-06-15 2024-10-22 Texas Instruments Incorporated Semiconductor structure and method for wafer scale chip package
KR102073295B1 (ko) 2018-06-22 2020-02-04 삼성전자주식회사 반도체 패키지
US11063146B2 (en) 2019-01-10 2021-07-13 Texas Instruments Incorporated Back-to-back power field-effect transistors with associated current sensors
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US10825789B1 (en) 2019-08-26 2020-11-03 Nxp B.V. Underbump metallization dimension variation with improved reliability
WO2021092779A1 (zh) * 2019-11-12 2021-05-20 华为技术有限公司 芯片堆叠封装结构、电子设备
KR20220056309A (ko) * 2020-10-27 2022-05-06 삼성전자주식회사 반도체 패키지
US11308257B1 (en) * 2020-12-15 2022-04-19 International Business Machines Corporation Stacked via rivets in chip hotspots
US11862576B2 (en) * 2021-10-28 2024-01-02 Texas Instruments Incorporated IC having electrically isolated warpage prevention structures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241889A (zh) * 2007-01-12 2008-08-13 硅存储技术公司 封装的凸点下金属层结构及其制造方法
CN101587873A (zh) * 2008-05-21 2009-11-25 福葆电子股份有限公司 降低应力的介电层结构及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462414B1 (en) * 1999-03-05 2002-10-08 Altera Corporation Integrated circuit package utilizing a conductive structure for interlocking a conductive ball to a ball pad
KR100306842B1 (ko) 1999-09-30 2001-11-02 윤종용 범프 패드에 오목 패턴이 형성된 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
JP3989152B2 (ja) * 2000-02-08 2007-10-10 株式会社リコー 半導体装置パッケージ
JP2003243569A (ja) * 2002-02-18 2003-08-29 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
JP3863161B2 (ja) * 2004-01-20 2006-12-27 松下電器産業株式会社 半導体装置
TWI268564B (en) * 2005-04-11 2006-12-11 Siliconware Precision Industries Co Ltd Semiconductor device and fabrication method thereof
KR100804392B1 (ko) 2005-12-02 2008-02-15 주식회사 네패스 반도체 패키지 및 그 제조 방법
KR100790527B1 (ko) 2006-07-27 2008-01-02 주식회사 네패스 웨이퍼레벨 패키지 및 그 제조 방법
JP2009010260A (ja) * 2007-06-29 2009-01-15 Fujikura Ltd 半導体装置
US20090278263A1 (en) 2008-05-09 2009-11-12 Texas Instruments Incorporated Reliability wcsp layouts
US8076786B2 (en) * 2008-07-11 2011-12-13 Advanced Semiconductor Engineering, Inc. Semiconductor package and method for packaging a semiconductor package
JP2010092930A (ja) * 2008-10-03 2010-04-22 Fujikura Ltd 半導体装置およびその製造方法
KR20100093357A (ko) 2009-02-16 2010-08-25 삼성전자주식회사 웨이퍼 레벨 칩스케일 패키지
US8084871B2 (en) * 2009-11-10 2011-12-27 Maxim Integrated Products, Inc. Redistribution layer enhancement to improve reliability of wafer level packaging

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101241889A (zh) * 2007-01-12 2008-08-13 硅存储技术公司 封装的凸点下金属层结构及其制造方法
CN101587873A (zh) * 2008-05-21 2009-11-25 福葆电子股份有限公司 降低应力的介电层结构及其制造方法

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