JP2010050283A - ウエハレベルcspにおける絶縁性テスト方法及びこれに用いるtegパターン - Google Patents
ウエハレベルcspにおける絶縁性テスト方法及びこれに用いるtegパターン Download PDFInfo
- Publication number
- JP2010050283A JP2010050283A JP2008213326A JP2008213326A JP2010050283A JP 2010050283 A JP2010050283 A JP 2010050283A JP 2008213326 A JP2008213326 A JP 2008213326A JP 2008213326 A JP2008213326 A JP 2008213326A JP 2010050283 A JP2010050283 A JP 2010050283A
- Authority
- JP
- Japan
- Prior art keywords
- teg
- pattern
- teg pattern
- spiral
- level csp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19042—Component type being an inductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Automation & Control Theory (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
【解決手段】本発明の第1の態様は、TEGパターンを用いたウエハレベルCSPの絶縁性テスト方法において、渦巻き状のTEGパターンを用いたことを特徴とする。また、本発明の第2の態様は、インダクタ素子を有するウエハレベルCSPの絶縁性テストに使用されるTEGパターンにおいて、前記TEGパターンは、渦巻き状に成形されていることを特徴とする。
【選択図】図3
Description
Element Group)パターンに関する。
112,212a,212b,314,414:TEGパターン
114,214a,214b:パターン形成領域
Claims (9)
- TEGパターンを用いたウエハレベルCSPの絶縁性テスト方法において、
渦巻き状のTEGパターンを用いたことを特徴とする絶縁性テスト方法。 - 前記ウエハレベルCSPは、インダクタ素子を有することを特徴とする請求項1に記載の絶縁性テスト方法。
- 前記TEGパターンは、テスト用のTEGチップ内に形成されていることを特徴とする請求項1又は2に記載の絶縁性テスト方法。
- 前記TEGパターンは、1つのチップにL/S(ライン・アンド・スペース)の異なる複数のパターンを有することを特徴とする請求項3に記載の絶縁性テスト方法。
- 前記TEGパターンは、通常のウエハレベルCSP用チップ内に形成されていることを特徴とする請求項1又は2に記載の絶縁性テスト方法。
- インダクタ素子を有するウエハレベルCSPの絶縁性テストに使用されるTEGパターンにおいて、
前記TEGパターンは、渦巻き状に成形されていることを特徴とするTEGパターン。 - 前記TEGパターンは、テスト用のTEGチップ内に形成されていることを特徴とする請求項5又は6に記載のTEGパターン。
- 前記TEGパターンは、1つのチップにL/S(ライン・アンド・スペース)の異なる複数のパターンを有することを特徴とする請求項7に記載のTEGパターン。
- 前記TEGパターンは、通常のウエハレベルCSP用チップ内に形成されていることを特徴とする請求項5又は6に記載のTEGパターン。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008213326A JP5414219B2 (ja) | 2008-08-21 | 2008-08-21 | ウエハレベルcspにおける絶縁性テスト方法及びこれに用いるtegパターン |
US12/511,375 US8237450B2 (en) | 2008-08-21 | 2009-07-29 | Method of testing insulation property of wafer-level chip scale package and TEG pattern used in the method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008213326A JP5414219B2 (ja) | 2008-08-21 | 2008-08-21 | ウエハレベルcspにおける絶縁性テスト方法及びこれに用いるtegパターン |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2010050283A true JP2010050283A (ja) | 2010-03-04 |
JP5414219B2 JP5414219B2 (ja) | 2014-02-12 |
Family
ID=41695762
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008213326A Expired - Fee Related JP5414219B2 (ja) | 2008-08-21 | 2008-08-21 | ウエハレベルcspにおける絶縁性テスト方法及びこれに用いるtegパターン |
Country Status (2)
Country | Link |
---|---|
US (1) | US8237450B2 (ja) |
JP (1) | JP5414219B2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI512851B (zh) * | 2012-09-01 | 2015-12-11 | Alpha & Omega Semiconductor | 帶有厚底部基座的晶圓級封裝器件及其製備方法 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9721854B2 (en) | 2012-12-05 | 2017-08-01 | International Business Machines Corporation | Structure and method for in-line defect non-contact tests |
KR20210000530A (ko) | 2019-06-25 | 2021-01-05 | 삼성전자주식회사 | 칩 적층 반도체 패키지 및 그 제조 방법 |
Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0574910A (ja) * | 1991-09-13 | 1993-03-26 | Fujitsu Ltd | 半導体集積回路装置 |
JPH05121908A (ja) * | 1991-10-30 | 1993-05-18 | Sharp Corp | マイクロ波回路 |
JPH07169816A (ja) * | 1993-12-16 | 1995-07-04 | Nec Corp | 半導体装置及びその選別方法 |
JP2002026100A (ja) * | 2000-07-04 | 2002-01-25 | Hitachi Ltd | 半導体基板および電気回路製造プロセスの検査方法並びに電気回路装置の製造方法 |
JP2003347410A (ja) * | 2002-05-27 | 2003-12-05 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005030822A (ja) * | 2003-07-09 | 2005-02-03 | Hitachi Ltd | 膜計測方法及びその装置 |
JP2005150452A (ja) * | 2003-11-17 | 2005-06-09 | Fujikura Ltd | 半導体パッケージの製造方法 |
JP2005340573A (ja) * | 2004-05-28 | 2005-12-08 | Fujikura Ltd | 半導体素子、半導体装置、及び半導体素子の製造方法 |
JP2007109989A (ja) * | 2005-10-17 | 2007-04-26 | Consortium For Advanced Semiconductor Materials & Related Technologies | Cmp方法 |
JP2007116041A (ja) * | 2005-10-24 | 2007-05-10 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
JP2007299904A (ja) * | 2006-04-28 | 2007-11-15 | Ebara Corp | 半導体装置及びその検査方法 |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3949976B2 (ja) * | 2001-04-04 | 2007-07-25 | 株式会社村田製作所 | 集中定数フィルタ、アンテナ共用器、および通信装置 |
-
2008
- 2008-08-21 JP JP2008213326A patent/JP5414219B2/ja not_active Expired - Fee Related
-
2009
- 2009-07-29 US US12/511,375 patent/US8237450B2/en not_active Expired - Fee Related
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0574910A (ja) * | 1991-09-13 | 1993-03-26 | Fujitsu Ltd | 半導体集積回路装置 |
JPH05121908A (ja) * | 1991-10-30 | 1993-05-18 | Sharp Corp | マイクロ波回路 |
JPH07169816A (ja) * | 1993-12-16 | 1995-07-04 | Nec Corp | 半導体装置及びその選別方法 |
JP2002026100A (ja) * | 2000-07-04 | 2002-01-25 | Hitachi Ltd | 半導体基板および電気回路製造プロセスの検査方法並びに電気回路装置の製造方法 |
JP2003347410A (ja) * | 2002-05-27 | 2003-12-05 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JP2005030822A (ja) * | 2003-07-09 | 2005-02-03 | Hitachi Ltd | 膜計測方法及びその装置 |
JP2005150452A (ja) * | 2003-11-17 | 2005-06-09 | Fujikura Ltd | 半導体パッケージの製造方法 |
JP2005340573A (ja) * | 2004-05-28 | 2005-12-08 | Fujikura Ltd | 半導体素子、半導体装置、及び半導体素子の製造方法 |
JP2007109989A (ja) * | 2005-10-17 | 2007-04-26 | Consortium For Advanced Semiconductor Materials & Related Technologies | Cmp方法 |
JP2007116041A (ja) * | 2005-10-24 | 2007-05-10 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
JP2007299904A (ja) * | 2006-04-28 | 2007-11-15 | Ebara Corp | 半導体装置及びその検査方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI512851B (zh) * | 2012-09-01 | 2015-12-11 | Alpha & Omega Semiconductor | 帶有厚底部基座的晶圓級封裝器件及其製備方法 |
Also Published As
Publication number | Publication date |
---|---|
US20100045304A1 (en) | 2010-02-25 |
US8237450B2 (en) | 2012-08-07 |
JP5414219B2 (ja) | 2014-02-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10950507B2 (en) | Electrical testing method of interposer | |
JP6008431B2 (ja) | Icデバイスのクラックアレストビア | |
JP6028298B2 (ja) | 半導体ダイ上にフィーチャをめっきするためのヒューズバス | |
US9048201B2 (en) | Sacrificial wafer probe pads through seal ring for electrical connection to circuit inside an integrated circuit | |
US10475760B2 (en) | Semiconductor device | |
JP2009246218A (ja) | 半導体装置の製造方法および半導体装置 | |
TW200937545A (en) | Semiconductor device and a method of manufacturing the same | |
CN105720027A (zh) | 半导体器件以及其制造方法 | |
JP2006210438A (ja) | 半導体装置およびその製造方法 | |
JP2010050224A (ja) | 半導体装置および半導体装置の製造方法 | |
KR101374148B1 (ko) | 반도체 패키지 및 이의 제조 방법 | |
US8901754B2 (en) | Semiconductor device and manufacturing method thereof | |
US9799571B2 (en) | Methods for producing integrated circuits with interposers and integrated circuits produced from such methods | |
KR100786210B1 (ko) | 반도체 장치 및 그 제조 방법 | |
JP5414219B2 (ja) | ウエハレベルcspにおける絶縁性テスト方法及びこれに用いるtegパターン | |
JP4446793B2 (ja) | 半導体装置およびその製造方法 | |
JP2006351767A (ja) | 半導体装置及びその製造方法 | |
KR20080088653A (ko) | 집적 회로 소자 및 그 제조 방법과, 집적 회로 및 그 제조 방법 | |
JP2006287094A (ja) | 半導体装置及びその製造方法 | |
JP6012688B2 (ja) | 半導体装置 | |
TWI795617B (zh) | 半導體元件 | |
JP2009231402A (ja) | 半導体装置及び半導体装置の製造方法 | |
JP6305375B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP2012160739A (ja) | 半導体装置 | |
JP2012253189A (ja) | 半導体装置の製造方法、及び半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20091202 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110817 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130418 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130423 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130620 |
|
RD03 | Notification of appointment of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7423 Effective date: 20130708 |
|
RD05 | Notification of revocation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7425 Effective date: 20130711 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130716 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130909 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20131112 |
|
LAPS | Cancellation because of no payment of annual fees |