JP6028298B2 - 半導体ダイ上にフィーチャをめっきするためのヒューズバス - Google Patents
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Description
シールリング又は他の連続的なダイ又はウエハ構造と、ダイの上面上の個々のボンドパッドとの間のヒューズめっきバス接続の実施形態を開示する。一実施形態は、シールリング構造の近くのウエハの能動層におけるポリシリコンヒューズを含む。シールリングの接点は、ポリヒューズの第1の端部に直接接続される。最上パッド導体層に電気的に結合された金属/ビアスタックは、ヒューズリンクの第2の端部に接続される。この金属/ビアスタックは、ボンドパッドフットプリントとシールリングとの間に配置されてもよく、ボンドパッドの直下に配置されてもよい。ウエハ上の複数のダイのシールリングが、スクライブストリート又はライン(後でソーイングプロセス中に除去される)に配置される共通の金属トレースに対する電気接続を介してひとまとめにされてもよい。
別の実施形態では、図1〜13に示し、本明細書に記載したように、半導体構造を形成する方法は、半導体基板302の上方にゲート電極304とヒューズ208とを形成する工程と、ゲート電極304とヒューズ208との上方に誘電体層314を形成する工程と、誘電体層314において、シールリング202の第1の部分と、ゲート電極304に対する接点306と、ヒューズ208の第1の端部又は端子に対する第1の接点308と、ヒューズ208の第2の端部又は端子に対する第2の接点310とを形成する工程と、誘電体層314の上方に相互接続層400〜408を形成する工程であって、相互接続層400〜408の形成は、相互接続層400〜408を通じて連続して延びるとともにシールリング202の第1の部分に接続されるシールリング202の第2の部分を形成することを含み、シールリング202は、相互接続層400〜408のうちの1つ以上の相互接続層を通じて第2の接点310に接続される、工程と、相互接続層400〜408の上方に相互接続パッド502を形成する工程であって、相互接続パッド502は相互接続層400〜408を通じて第1の接点308に接続される、工程と、を含む。
さらなる一態様では、ゲート電極304と、ヒューズ208と、相互接続パッド502と、シールリング202とは、第1のダイ102内に存在し、ゲート電極304及びヒューズ208を形成する工程は、第1のダイ102に隣接する第2のダイ102において半導体基板の上方に第2のヒューズ320を形成する工程を含み、誘電体層314は第2のヒューズ320の上方に形成される。シールリング202の第1の部分と、ゲート電極304に対する接点306と、ヒューズ208の第1の端部又は端子に対する第1の接点308と、ヒューズ208の第2の端部又は端子に対する第2の接点310とを形成する工程は、誘電体層314において、第2のシールリング202の第1の部分と、第2のヒューズ320の第1の端部又は端子に対する第1の接点308と、第2のヒューズ320の第2の端部又は端子に対する第2の接点318とを形成する工程を含む。相互接続層400〜408を形成する工程は、複数の相互接続層400〜408を通じて連続して延びるとともに第2のシールリング202の第1の部分に接続される第2のシールリング202の第2の部分を形成する工程であって、第2のシールリング202は、相互接続層400〜408のうちの1つ以上の相互接続層を通じて第2のヒューズ320の第2の端部又は端子に対する第2の接点318に接続される、工程を含む。相互接続パッド502を形成する工程は、相互接続層400〜408の上方に第2の相互接続パッド502を形成する工程を含み、第2の相互接続パッド502は、相互接続層400〜408を通じて第2のヒューズ320の第1の端部又は端子の第1の接点に接続され、第2のヒューズ320と、第2の相互接続パッド502と、第2のシールリング202とは、第2のダイ102内に存在する。
Claims (4)
- 能動回路を包囲するシールリングを備えた複数のダイからなる半導体構造の製造方法において、
半導体基板の上方にゲート電極とヒューズとを形成する工程と、
前記ゲート電極と前記ヒューズとの上方に誘電体層を形成する工程と、
前記誘電体層において、シールリングの第1の部分と、前記ゲート電極に対する接点と、前記ヒューズの第1の端子に対する第1の接点と、前記ヒューズの第2の端子に対する第2の接点とを形成する工程と、
前記誘電体層の上方に複数の相互接続層を形成する工程であって、該工程は、前記複数の相互接続層を通じて連続して延びるとともに前記シールリングの前記第1の部分に接続される前記シールリングの第2の部分を形成する工程を含み、前記シールリングは、前記複数の相互接続層のうちの1つ以上の相互接続層を通じて前記ヒューズの第2の接点に接続される、前記誘電体層の上方に複数の相互接続層を形成する工程と、
前記複数の相互接続層の上方に相互接続パッドを形成する工程であって、該相互接続パッドは前記複数の相互接続層を通じて前記第1の接点に接続される、前記複数の相互接続層の上方に相互接続パッドを形成する工程と、
隣接するダイのそれぞれのシールリングの間に設けられたスクライブストリートで前記隣接するダイを互いから分離すべく、前記複数のダイを個片化する工程と
を備え、個片化した前記ダイを前記シールリングによって汚染イオンから保護する、半導体構造の製造方法。 - 前記シールリングは前記シールリングの第1の部分を含んでなるクラック停止部を有し、前記クラック停止部は前記複数のダイを個片化する工程において生成されるクラックが前記能動回路に入り込むことを防止する、請求項1に記載の半導体構造の製造方法。
- 前記複数の相互接続層の上方に相互接続パッドを形成する工程よりも後に、前記シールリング及び前記複数のヒューズの各々を通じて前記複数の相互接続パッドの各々に電流を提供し、前記複数の相互接続パッドの各々の上に導体層を電気めっきする電気めっき工程をさらに備える、請求項1に記載の半導体構造の製造方法。
- 前記複数のダイを個片化する工程よりも前にそれぞれの前記相互接続パッドに電流を印加して前記半導体構造のウエハ試験を実施する工程をさらに備え、前記電流は前記ヒューズを故障させ、前記能動回路と前記シールリングの間に開回路を形成するために十分である、請求項1に記載の半導体構造の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US13/189,054 US8349666B1 (en) | 2011-07-22 | 2011-07-22 | Fused buss for plating features on a semiconductor die |
US13/189,054 | 2011-07-22 |
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JP2013026624A JP2013026624A (ja) | 2013-02-04 |
JP2013026624A5 JP2013026624A5 (ja) | 2015-09-03 |
JP6028298B2 true JP6028298B2 (ja) | 2016-11-16 |
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JP2012159145A Active JP6028298B2 (ja) | 2011-07-22 | 2012-07-18 | 半導体ダイ上にフィーチャをめっきするためのヒューズバス |
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US (1) | US8349666B1 (ja) |
EP (1) | EP2549532B1 (ja) |
JP (1) | JP6028298B2 (ja) |
TW (1) | TWI538152B (ja) |
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US20130023091A1 (en) | 2013-01-24 |
US8349666B1 (en) | 2013-01-08 |
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JP2013026624A (ja) | 2013-02-04 |
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