JP2017506001A5 - - Google Patents
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- Publication number
- JP2017506001A5 JP2017506001A5 JP2016550864A JP2016550864A JP2017506001A5 JP 2017506001 A5 JP2017506001 A5 JP 2017506001A5 JP 2016550864 A JP2016550864 A JP 2016550864A JP 2016550864 A JP2016550864 A JP 2016550864A JP 2017506001 A5 JP2017506001 A5 JP 2017506001A5
- Authority
- JP
- Japan
- Prior art keywords
- level die
- wafer level
- interconnects
- wafer
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims 11
- 229910000679 solder Inorganic materials 0.000 claims 4
- 239000000758 substrate Substances 0.000 claims 4
- 238000005538 encapsulation Methods 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/181,371 | 2014-02-14 | ||
| US14/181,371 US9583460B2 (en) | 2014-02-14 | 2014-02-14 | Integrated device comprising stacked dies on redistribution layers |
| PCT/US2015/015639 WO2015123426A2 (en) | 2014-02-14 | 2015-02-12 | Integrated device comprising stacked dies on redistribution layers |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018002530A Division JP2018082205A (ja) | 2014-02-14 | 2018-01-11 | 再分配層上に積層ダイを備える集積デバイス |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017506001A JP2017506001A (ja) | 2017-02-23 |
| JP2017506001A5 true JP2017506001A5 (enExample) | 2017-06-08 |
| JP6309643B2 JP6309643B2 (ja) | 2018-04-11 |
Family
ID=52686444
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016550864A Active JP6309643B2 (ja) | 2014-02-14 | 2015-02-12 | 再分配層上に積層ダイを備える集積デバイス |
| JP2018002530A Pending JP2018082205A (ja) | 2014-02-14 | 2018-01-11 | 再分配層上に積層ダイを備える集積デバイス |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018002530A Pending JP2018082205A (ja) | 2014-02-14 | 2018-01-11 | 再分配層上に積層ダイを備える集積デバイス |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US9583460B2 (enExample) |
| EP (1) | EP3105789B1 (enExample) |
| JP (2) | JP6309643B2 (enExample) |
| KR (1) | KR101872510B1 (enExample) |
| CN (2) | CN110060974B (enExample) |
| BR (1) | BR112016018580B1 (enExample) |
| CA (1) | CA2937552C (enExample) |
| ES (1) | ES2910956T3 (enExample) |
| WO (1) | WO2015123426A2 (enExample) |
Families Citing this family (24)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9852998B2 (en) * | 2014-05-30 | 2017-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Ring structures in device die |
| US9842825B2 (en) | 2014-09-05 | 2017-12-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrateless integrated circuit packages and methods of forming same |
| JP6330788B2 (ja) * | 2015-11-18 | 2018-05-30 | 株式会社村田製作所 | 電子デバイス |
| US10403609B2 (en) | 2015-12-21 | 2019-09-03 | Intel IP Corporation | System-in-package devices and methods for forming system-in-package devices |
| US10276402B2 (en) * | 2016-03-21 | 2019-04-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and manufacturing process thereof |
| US10134708B2 (en) * | 2016-08-05 | 2018-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package with thinned substrate |
| CN116190326A (zh) * | 2016-12-29 | 2023-05-30 | 英特尔公司 | 超芯片 |
| US10854568B2 (en) | 2017-04-07 | 2020-12-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with Si-substrate-free interposer and method forming same |
| DE102017124104B4 (de) | 2017-04-07 | 2025-05-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Packages mit si-substrat-freiem interposer und verfahren zum bilden derselben |
| US10522449B2 (en) | 2017-04-10 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with Si-substrate-free interposer and method forming same |
| DE102017123449B4 (de) | 2017-04-10 | 2023-12-28 | Taiwan Semiconductor Manufacturing Co. Ltd. | Gehäuse mit Si-substratfreiem Zwischenstück und Ausbildungsverfahren |
| CN107226452B (zh) * | 2017-05-24 | 2019-05-31 | 中国科学院上海微系统与信息技术研究所 | 共面键合结构及其制备方法 |
| KR102412613B1 (ko) | 2017-07-24 | 2022-06-23 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
| CN108807361B (zh) * | 2017-07-25 | 2022-03-04 | 长鑫存储技术有限公司 | 一种芯片堆栈立体封装结构 |
| US10290571B2 (en) | 2017-09-18 | 2019-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Packages with si-substrate-free interposer and method forming same |
| DE112017008093T5 (de) * | 2017-09-25 | 2020-07-02 | Intel Corporation | Monolithische chip-stapelung unter verwendung eines dies mit doppelseitigen verbindungsschichten |
| US10790300B2 (en) | 2019-03-01 | 2020-09-29 | Sandisk Technologies Llc | Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same |
| US11424231B2 (en) | 2019-03-01 | 2022-08-23 | Sandisk Technologies Llc | Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same |
| US11398451B2 (en) | 2019-03-01 | 2022-07-26 | Sandisk Technologies Llc | Methods for reusing substrates during manufacture of a bonded assembly including a logic die and a memory die |
| US11239253B2 (en) | 2019-03-01 | 2022-02-01 | Sandisk Technologies Llc | Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same |
| US11410902B2 (en) | 2019-09-16 | 2022-08-09 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| US11217560B2 (en) * | 2019-10-28 | 2022-01-04 | Nanya Technology Corporation | Die assembly and method of manufacturing the same |
| US11784151B2 (en) * | 2020-07-22 | 2023-10-10 | Qualcomm Incorporated | Redistribution layer connection |
| WO2022016470A1 (zh) * | 2020-07-23 | 2022-01-27 | 华为技术有限公司 | 一种芯片封装结构、电子设备 |
Family Cites Families (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3011098U (ja) * | 1994-11-11 | 1995-05-16 | 勝規 森 | 取付具付き水準器 |
| JP2000155027A (ja) * | 1998-11-19 | 2000-06-06 | Komatsu Ltd | 水準器 |
| JP2003344047A (ja) * | 2002-05-27 | 2003-12-03 | Hokuriku Seiko:Kk | 遊技盤面傾斜器 |
| US20070126085A1 (en) | 2005-12-02 | 2007-06-07 | Nec Electronics Corporation | Semiconductor device and method of manufacturing the same |
| KR100753415B1 (ko) | 2006-03-17 | 2007-08-30 | 주식회사 하이닉스반도체 | 스택 패키지 |
| JP2008091639A (ja) * | 2006-10-02 | 2008-04-17 | Nec Electronics Corp | 電子装置およびその製造方法 |
| JP2008091638A (ja) * | 2006-10-02 | 2008-04-17 | Nec Electronics Corp | 電子装置およびその製造方法 |
| US7969009B2 (en) * | 2008-06-30 | 2011-06-28 | Qualcomm Incorporated | Through silicon via bridge interconnect |
| US8446017B2 (en) * | 2009-09-18 | 2013-05-21 | Amkor Technology Korea, Inc. | Stackable wafer level package and fabricating method thereof |
| US9431316B2 (en) * | 2010-05-04 | 2016-08-30 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming channels in back surface of FO-WLCSP for heat dissipation |
| TWI427753B (zh) * | 2010-05-20 | 2014-02-21 | 日月光半導體製造股份有限公司 | 封裝結構以及封裝製程 |
| US9620455B2 (en) | 2010-06-24 | 2017-04-11 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure |
| KR101683814B1 (ko) | 2010-07-26 | 2016-12-08 | 삼성전자주식회사 | 관통 전극을 구비하는 반도체 장치 |
| US8754516B2 (en) * | 2010-08-26 | 2014-06-17 | Intel Corporation | Bumpless build-up layer package with pre-stacked microelectronic devices |
| US8786066B2 (en) * | 2010-09-24 | 2014-07-22 | Intel Corporation | Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same |
| US9224647B2 (en) * | 2010-09-24 | 2015-12-29 | Stats Chippac, Ltd. | Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer |
| US8993377B2 (en) * | 2010-09-29 | 2015-03-31 | Stats Chippac, Ltd. | Semiconductor device and method of bonding different size semiconductor die at the wafer level |
| US8421245B2 (en) * | 2010-12-22 | 2013-04-16 | Intel Corporation | Substrate with embedded stacked through-silicon via die |
| US8648470B2 (en) * | 2011-01-21 | 2014-02-11 | Stats Chippac, Ltd. | Semiconductor device and method of forming FO-WLCSP with multiple encapsulants |
| JP5716415B2 (ja) * | 2011-01-26 | 2015-05-13 | 富士通株式会社 | 半導体装置の製造方法 |
| JP2012227443A (ja) * | 2011-04-21 | 2012-11-15 | Sumitomo Bakelite Co Ltd | 半導体装置の製造方法および半導体装置 |
| KR101739945B1 (ko) | 2011-05-02 | 2017-06-09 | 삼성전자주식회사 | 반도체 패키지 및 이를 제조하는 방법 |
| KR20130015885A (ko) | 2011-08-05 | 2013-02-14 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
| US8754514B2 (en) * | 2011-08-10 | 2014-06-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip wafer level package |
| JP2013038300A (ja) | 2011-08-10 | 2013-02-21 | Fujitsu Ltd | 電子装置及びその製造方法 |
| JP2013045863A (ja) * | 2011-08-24 | 2013-03-04 | Elpida Memory Inc | 半導体装置およびその製造方法 |
| KR101906408B1 (ko) * | 2011-10-04 | 2018-10-11 | 삼성전자주식회사 | 반도체 패키지 및 그 제조 방법 |
| US10475759B2 (en) * | 2011-10-11 | 2019-11-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit structure having dies with connectors of different sizes |
| JP6103470B2 (ja) * | 2011-12-14 | 2017-03-29 | 川崎化成工業株式会社 | 縮合多環芳香族骨格を有する連鎖移動剤並びに該縮合多環芳香族骨格を有するポリマーおよびポリマーの製造方法 |
| US8546955B1 (en) | 2012-08-16 | 2013-10-01 | Xilinx, Inc. | Multi-die stack package |
| US9165887B2 (en) * | 2012-09-10 | 2015-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device with discrete blocks |
| US9478474B2 (en) * | 2012-12-28 | 2016-10-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for forming package-on-packages |
| US9524942B2 (en) * | 2013-12-18 | 2016-12-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Chip-on-substrate packaging on carrier |
| JP6551903B2 (ja) * | 2015-06-29 | 2019-07-31 | 株式会社スリーストン | 傾斜計 |
| JP6799914B2 (ja) * | 2015-12-10 | 2020-12-16 | 大都販売株式会社 | 傾斜計、遊技機傾斜測定方法 |
-
2014
- 2014-02-14 US US14/181,371 patent/US9583460B2/en active Active
-
2015
- 2015-02-12 CN CN201910374357.9A patent/CN110060974B/zh active Active
- 2015-02-12 ES ES15710617T patent/ES2910956T3/es active Active
- 2015-02-12 KR KR1020167024802A patent/KR101872510B1/ko active Active
- 2015-02-12 CA CA2937552A patent/CA2937552C/en active Active
- 2015-02-12 WO PCT/US2015/015639 patent/WO2015123426A2/en not_active Ceased
- 2015-02-12 BR BR112016018580-3A patent/BR112016018580B1/pt active IP Right Grant
- 2015-02-12 CN CN201580008254.0A patent/CN106133897B/zh active Active
- 2015-02-12 EP EP15710617.0A patent/EP3105789B1/en active Active
- 2015-02-12 JP JP2016550864A patent/JP6309643B2/ja active Active
-
2018
- 2018-01-11 JP JP2018002530A patent/JP2018082205A/ja active Pending
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