JP2016518730A5 - - Google Patents

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Publication number
JP2016518730A5
JP2016518730A5 JP2016515351A JP2016515351A JP2016518730A5 JP 2016518730 A5 JP2016518730 A5 JP 2016518730A5 JP 2016515351 A JP2016515351 A JP 2016515351A JP 2016515351 A JP2016515351 A JP 2016515351A JP 2016518730 A5 JP2016518730 A5 JP 2016518730A5
Authority
JP
Japan
Prior art keywords
layer
insulating layer
kide
mold
providing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016515351A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016518730A (ja
Filing date
Publication date
Priority claimed from US13/898,427 external-priority patent/US10141202B2/en
Application filed filed Critical
Publication of JP2016518730A publication Critical patent/JP2016518730A/ja
Publication of JP2016518730A5 publication Critical patent/JP2016518730A5/ja
Pending legal-status Critical Current

Links

JP2016515351A 2013-05-20 2014-05-12 上面および側壁保護のためのモールドを備える半導体デバイス Pending JP2016518730A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/898,427 2013-05-20
US13/898,427 US10141202B2 (en) 2013-05-20 2013-05-20 Semiconductor device comprising mold for top side and sidewall protection
PCT/US2014/037739 WO2014189704A1 (en) 2013-05-20 2014-05-12 Semiconductor device comprising mold for top side and sidewall protection

Publications (2)

Publication Number Publication Date
JP2016518730A JP2016518730A (ja) 2016-06-23
JP2016518730A5 true JP2016518730A5 (enExample) 2017-06-15

Family

ID=50897962

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016515351A Pending JP2016518730A (ja) 2013-05-20 2014-05-12 上面および側壁保護のためのモールドを備える半導体デバイス

Country Status (5)

Country Link
US (1) US10141202B2 (enExample)
EP (1) EP3000128B1 (enExample)
JP (1) JP2016518730A (enExample)
CN (1) CN105229784A (enExample)
WO (1) WO2014189704A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10720495B2 (en) * 2014-06-12 2020-07-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US10128207B2 (en) * 2015-03-31 2018-11-13 Stmicroelectronics Pte Ltd Semiconductor packages with pillar and bump structures
CN106505055B (zh) * 2015-09-08 2019-08-27 中芯国际集成电路制造（天津）有限公司 半导体结构及其形成方法
JP2020074352A (ja) * 2017-03-13 2020-05-14 三菱電機株式会社 半導体装置
US20190131247A1 (en) * 2017-10-31 2019-05-02 Microchip Technology Incorporated Semiconductor Wafer Cutting Using A Polymer Coating To Reduce Physical Damage
KR102600001B1 (ko) 2018-10-18 2023-11-08 삼성전자주식회사 스크라이브 레인을 포함하는 반도체 칩
US12113038B2 (en) * 2020-01-03 2024-10-08 Qualcomm Incorporated Thermal compression flip chip bump for high performance and fine pitch
US12021013B2 (en) * 2021-01-29 2024-06-25 Mediatek Inc. Ball pad design for semiconductor packages
KR20240012398A (ko) * 2021-05-25 2024-01-29 소니 세미컨덕터 솔루션즈 가부시키가이샤 반도체 패키지 및 전자 기기
US11887955B2 (en) * 2021-08-26 2024-01-30 Taiwan Semiconductor Manufacturing Company Limited Semiconductor die including stress-resistant bonding structures and methods of forming the same

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6181569B1 (en) 1999-06-07 2001-01-30 Kishore K. Chakravorty Low cost chip size package and method of fabricating the same
JP3770007B2 (ja) 1999-11-01 2006-04-26 凸版印刷株式会社 半導体装置の製造方法
JP2001144213A (ja) 1999-11-16 2001-05-25 Hitachi Ltd 半導体装置の製造方法および半導体装置
US6607941B2 (en) * 2002-01-11 2003-08-19 National Semiconductor Corporation Process and structure improvements to shellcase style packaging technology
TWI226090B (en) 2003-09-26 2005-01-01 Advanced Semiconductor Eng Transparent packaging in wafer level
JP4519571B2 (ja) 2004-08-26 2010-08-04 ルネサスエレクトロニクス株式会社 半導体装置及びその検査方法と検査装置並びに半導体装置の製造方法
US7160756B2 (en) * 2004-10-12 2007-01-09 Agency For Science, Techology And Research Polymer encapsulated dicing lane (PEDL) technology for Cu/low/ultra-low k devices
WO2006054606A1 (ja) * 2004-11-16 2006-05-26 Rohm Co., Ltd. 半導体装置および半導体装置の製造方法
US9034731B2 (en) 2005-02-03 2015-05-19 Stats Chippac Ltd. Integrated, integrated circuit singulation system
KR100652443B1 (ko) 2005-11-17 2006-12-01 삼성전자주식회사 재배선층을 갖는 웨이퍼 레벨 패키지 및 그 형성방법
US7723225B2 (en) * 2006-02-07 2010-05-25 Stats Chippac Ltd. Solder bump confinement system for an integrated circuit package
JP4193897B2 (ja) * 2006-05-19 2008-12-10 カシオ計算機株式会社 半導体装置およびその製造方法
TWI419268B (zh) 2007-09-21 2013-12-11 兆裝微股份有限公司 半導體裝置及其製造方法
KR100887479B1 (ko) 2007-10-09 2009-03-10 주식회사 네패스 내균열성 반도체 패키지 및 그 제조 방법
JP2009111333A (ja) 2007-10-12 2009-05-21 Panasonic Corp 半導体装置
US8048776B2 (en) 2008-02-22 2011-11-01 Stats Chippac, Ltd. Semiconductor device and method of supporting a wafer during backgrinding and reflow of solder bumps
JP4666028B2 (ja) * 2008-03-31 2011-04-06 カシオ計算機株式会社 半導体装置
CN101552248B (zh) * 2008-03-31 2013-01-23 兆装微股份有限公司 半导体装置及其制造方法
KR20090123280A (ko) * 2008-05-27 2009-12-02 삼성전자주식회사 반도체 칩 패키지의 제조 방법, 반도체 웨이퍼 및 그 절단방법
US8580657B2 (en) * 2008-09-23 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Protecting sidewalls of semiconductor chips using insulation films
US7977783B1 (en) 2009-08-27 2011-07-12 Amkor Technology, Inc. Wafer level chip size package having redistribution layers
FR2953064B1 (fr) 2009-11-20 2011-12-16 St Microelectronics Tours Sas Procede d'encapsulation de composants electroniques sur tranche
US8287996B2 (en) 2009-12-21 2012-10-16 Intel Corporation Coating for a microelectronic device, treatment comprising same, and method of managing a thermal profile of a microelectronic die
JP5553642B2 (ja) 2010-02-24 2014-07-16 株式会社テラプローブ 半導体装置の製造方法及び薄型化基板の製造方法
US8304867B2 (en) 2010-11-01 2012-11-06 Texas Instruments Incorporated Crack arrest vias for IC devices
US8048778B1 (en) * 2010-12-10 2011-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of dicing a semiconductor structure
US8786081B2 (en) * 2011-07-27 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method and device for circuit routing by way of under-bump metallization
US20130320522A1 (en) * 2012-05-30 2013-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Re-distribution Layer Via Structure and Method of Making Same
US9275924B2 (en) 2012-08-14 2016-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having a recess filled with a molding compound

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