JP2017507495A5 - - Google Patents

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Publication number
JP2017507495A5
JP2017507495A5 JP2016555342A JP2016555342A JP2017507495A5 JP 2017507495 A5 JP2017507495 A5 JP 2017507495A5 JP 2016555342 A JP2016555342 A JP 2016555342A JP 2016555342 A JP2016555342 A JP 2016555342A JP 2017507495 A5 JP2017507495 A5 JP 2017507495A5
Authority
JP
Japan
Prior art keywords
die
base portion
interconnect pillars
integrated device
interconnects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016555342A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017507495A (ja
Filing date
Publication date
Priority claimed from US14/196,817 external-priority patent/US9230936B2/en
Application filed filed Critical
Publication of JP2017507495A publication Critical patent/JP2017507495A/ja
Publication of JP2017507495A5 publication Critical patent/JP2017507495A5/ja
Pending legal-status Critical Current

Links

JP2016555342A 2014-03-04 2015-03-04 高密度インターコネクトおよび再分配層を備える集積デバイス Pending JP2017507495A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/196,817 US9230936B2 (en) 2014-03-04 2014-03-04 Integrated device comprising high density interconnects and redistribution layers
US14/196,817 2014-03-04
PCT/US2015/018784 WO2015134638A1 (en) 2014-03-04 2015-03-04 Integrated device comprising high density interconnects and redistribution layers

Publications (2)

Publication Number Publication Date
JP2017507495A JP2017507495A (ja) 2017-03-16
JP2017507495A5 true JP2017507495A5 (enExample) 2018-03-29

Family

ID=52684720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016555342A Pending JP2017507495A (ja) 2014-03-04 2015-03-04 高密度インターコネクトおよび再分配層を備える集積デバイス

Country Status (5)

Country Link
US (1) US9230936B2 (enExample)
EP (1) EP3114707A1 (enExample)
JP (1) JP2017507495A (enExample)
CN (1) CN106068558A (enExample)
WO (1) WO2015134638A1 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018009145A1 (en) * 2016-07-08 2018-01-11 Agency For Science, Technology And Research A semiconductor package and methods of forming the same
WO2018063263A1 (en) * 2016-09-29 2018-04-05 Intel Corporation Panel level packaging for multi-die products interconnected with very high density (vhd) interconnect layers
US10727185B2 (en) 2016-09-30 2020-07-28 Intel Corporation Multi-chip package with high density interconnects
US9799618B1 (en) * 2016-10-12 2017-10-24 International Business Machines Corporation Mixed UBM and mixed pitch on a single die
US11152274B2 (en) * 2017-09-11 2021-10-19 Advanced Semiconductor Engineering, Inc. Multi-moldings fan-out package and process
US10181449B1 (en) * 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
KR102124892B1 (ko) * 2017-09-29 2020-06-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 팬-아웃 패키징 공정에서의 범프 정렬
US11217555B2 (en) * 2017-09-29 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Aligning bumps in fan-out packaging process
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
US10679946B2 (en) * 2018-04-10 2020-06-09 Wispry, Inc. Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates
US10665673B2 (en) 2018-06-28 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure with non-gated well tap cell
US11322450B2 (en) 2018-10-18 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package and method of forming the same
US11605594B2 (en) * 2020-03-23 2023-03-14 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate
US11832391B2 (en) * 2020-09-30 2023-11-28 Qualcomm Incorporated Terminal connection routing and method the same
US11705420B2 (en) * 2020-10-29 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-bump connection to interconnect structure and manufacturing method thereof
CN112420531B (zh) * 2020-11-27 2021-11-30 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
CN113169075B (zh) * 2021-02-08 2022-06-03 广东省科学院半导体研究所 一种芯片互连封装结构及方法
US11869833B2 (en) * 2021-09-15 2024-01-09 Qualcomm Incorporated Package comprising a substrate with a via interconnect coupled to a trace interconnect and method of fabricating the same
CN118202460A (zh) * 2021-11-05 2024-06-14 美商艾德亚半导体接合科技有限公司 多沟道器件堆叠

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JP3728847B2 (ja) * 1997-02-04 2005-12-21 株式会社日立製作所 マルチチップモジュールおよびその製造方法
US8574959B2 (en) * 2003-11-10 2013-11-05 Stats Chippac, Ltd. Semiconductor device and method of forming bump-on-lead interconnection
JP2008091638A (ja) * 2006-10-02 2008-04-17 Nec Electronics Corp 電子装置およびその製造方法
US20080142946A1 (en) * 2006-12-13 2008-06-19 Advanced Chip Engineering Technology Inc. Wafer level package with good cte performance
JP2009059771A (ja) * 2007-08-30 2009-03-19 Kyushu Institute Of Technology ウエハレベルチップサイズパッケージ及びその製造方法
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
KR101214746B1 (ko) * 2008-09-03 2012-12-21 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
JP5173758B2 (ja) * 2008-11-17 2013-04-03 新光電気工業株式会社 半導体パッケージの製造方法
US8406004B2 (en) * 2008-12-09 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
US8110926B2 (en) * 2009-01-30 2012-02-07 Broadcom Corporation Redistribution layer power grid
US8378383B2 (en) * 2009-03-25 2013-02-19 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
TWI528514B (zh) * 2009-08-20 2016-04-01 精材科技股份有限公司 晶片封裝體及其製造方法
US8901724B2 (en) * 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
US8742561B2 (en) * 2009-12-29 2014-06-03 Intel Corporation Recessed and embedded die coreless package
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US9620455B2 (en) 2010-06-24 2017-04-11 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming anisotropic conductive film between semiconductor die and build-up interconnect structure
US8796137B2 (en) 2010-06-24 2014-08-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect
US8426961B2 (en) * 2010-06-25 2013-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded 3D interposer structure
US8691626B2 (en) * 2010-09-09 2014-04-08 Advanced Micro Devices, Inc. Semiconductor chip device with underfill
US8435834B2 (en) * 2010-09-13 2013-05-07 Stats Chippac, Ltd. Semiconductor device and method of forming bond-on-lead interconnection for mounting semiconductor die in FO-WLCSP
US8786066B2 (en) * 2010-09-24 2014-07-22 Intel Corporation Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming same
US8384225B2 (en) 2010-11-12 2013-02-26 Xilinx, Inc. Through silicon via with improved reliability
US8754514B2 (en) * 2011-08-10 2014-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip wafer level package
US9786622B2 (en) * 2011-10-20 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package
JP2013153122A (ja) * 2011-10-20 2013-08-08 Nitto Denko Corp 半導体装置の製造方法
US20130099371A1 (en) * 2011-10-21 2013-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package having solder jointed region with controlled ag content
US9748203B2 (en) 2011-12-15 2017-08-29 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8558395B2 (en) 2012-02-21 2013-10-15 Broadcom Corporation Organic interface substrate having interposer with through-semiconductor vias
US8878360B2 (en) * 2012-07-13 2014-11-04 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip

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