CN106068558A - 包括高密度互连和重分布层的集成器件 - Google Patents

包括高密度互连和重分布层的集成器件 Download PDF

Info

Publication number
CN106068558A
CN106068558A CN201580011603.4A CN201580011603A CN106068558A CN 106068558 A CN106068558 A CN 106068558A CN 201580011603 A CN201580011603 A CN 201580011603A CN 106068558 A CN106068558 A CN 106068558A
Authority
CN
China
Prior art keywords
die
interconnects
implementations
integrated device
redistribution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201580011603.4A
Other languages
English (en)
Chinese (zh)
Inventor
D·W·金
H·B·蔚
J·S·李
S·顾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN106068558A publication Critical patent/CN106068558A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/14335—Digital signal processor [DSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1434—Memory
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
CN201580011603.4A 2014-03-04 2015-03-04 包括高密度互连和重分布层的集成器件 Pending CN106068558A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/196,817 US9230936B2 (en) 2014-03-04 2014-03-04 Integrated device comprising high density interconnects and redistribution layers
US14/196,817 2014-03-04
PCT/US2015/018784 WO2015134638A1 (en) 2014-03-04 2015-03-04 Integrated device comprising high density interconnects and redistribution layers

Publications (1)

Publication Number Publication Date
CN106068558A true CN106068558A (zh) 2016-11-02

Family

ID=52684720

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580011603.4A Pending CN106068558A (zh) 2014-03-04 2015-03-04 包括高密度互连和重分布层的集成器件

Country Status (5)

Country Link
US (1) US9230936B2 (enExample)
EP (1) EP3114707A1 (enExample)
JP (1) JP2017507495A (enExample)
CN (1) CN106068558A (enExample)
WO (1) WO2015134638A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109494162A (zh) * 2017-09-11 2019-03-19 日月光半导体制造股份有限公司 多模件扇出型封装及工艺
CN112420531A (zh) * 2020-11-27 2021-02-26 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
WO2022165854A1 (zh) * 2021-02-08 2022-08-11 广东省科学院半导体研究所 一种芯片互连封装结构及方法
CN115298819A (zh) * 2020-03-23 2022-11-04 高通股份有限公司 包括衬底以及与衬底耦合的高密度互连集成器件的封装件

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018009145A1 (en) * 2016-07-08 2018-01-11 Agency For Science, Technology And Research A semiconductor package and methods of forming the same
US11101222B2 (en) * 2016-09-29 2021-08-24 Intel Corporation Panel level packaging for multi-die products interconnected with very high density (VHD) interconnect layers
WO2018063400A1 (en) * 2016-09-30 2018-04-05 Intel Corporation Multi-chip package with high density interconnects
US9799618B1 (en) * 2016-10-12 2017-10-24 International Business Machines Corporation Mixed UBM and mixed pitch on a single die
US10181449B1 (en) * 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
US11217555B2 (en) * 2017-09-29 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Aligning bumps in fan-out packaging process
KR102124892B1 (ko) * 2017-09-29 2020-06-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 팬-아웃 패키징 공정에서의 범프 정렬
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
WO2019199966A1 (en) * 2018-04-10 2019-10-17 Wispry, Inc. Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates
US10665673B2 (en) 2018-06-28 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure with non-gated well tap cell
US11322450B2 (en) 2018-10-18 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package and method of forming the same
US11832391B2 (en) * 2020-09-30 2023-11-28 Qualcomm Incorporated Terminal connection routing and method the same
US11705420B2 (en) * 2020-10-29 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-bump connection to interconnect structure and manufacturing method thereof
US11869833B2 (en) * 2021-09-15 2024-01-09 Qualcomm Incorporated Package comprising a substrate with a via interconnect coupled to a trace interconnect and method of fabricating the same
KR20240094026A (ko) * 2021-11-05 2024-06-24 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 멀티-채널 디바이스 스태킹

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101159240A (zh) * 2006-10-02 2008-04-09 恩益禧电子股份有限公司 电子设备和制造电子设备的方法
US20100123239A1 (en) * 2008-11-17 2010-05-20 Shinko Electric Industries Co., Ltd. Semiconductor package and method of manufacturing the same
US20110042796A1 (en) * 2009-08-20 2011-02-24 Shu-Ming Chang Chip package and fabrication method thereof
CN102299143A (zh) * 2010-06-25 2011-12-28 台湾积体电路制造股份有限公司 半导体元件
US20110316146A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Anisotropic Conductive Film Between Semiconductor Die and Build-Up Interconnect Structure
US20110316156A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
CN102403239A (zh) * 2010-09-13 2012-04-04 新科金朋有限公司 半导体器件及形成用于在Fo-WLCSP中安装半导体小片的引线上键合互连的方法
CN102487020A (zh) * 2010-12-03 2012-06-06 新科金朋有限公司 形成引线上凸块互连的半导体器件和方法
CN102640283A (zh) * 2009-12-29 2012-08-15 英特尔公司 具有嵌入式管芯的半导体封装及其制造方法
CN102656686A (zh) * 2009-12-29 2012-09-05 英特尔公司 凹陷型嵌入式管芯无核封装
CN102931173A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装
CN103066050A (zh) * 2011-10-21 2013-04-24 台湾积体电路制造股份有限公司 具有银含量可控的焊料接合区域的半导体封装件
CN103066043A (zh) * 2011-10-20 2013-04-24 台湾积体电路制造股份有限公司 半导体封装件
CN103119712A (zh) * 2010-09-24 2013-05-22 英特尔公司 使用在包括嵌入式管芯的内建非凹凸层衬底上的硅通孔的管芯堆叠,以及其形成工艺
US20140015131A1 (en) * 2012-07-13 2014-01-16 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JP3728847B2 (ja) * 1997-02-04 2005-12-21 株式会社日立製作所 マルチチップモジュールおよびその製造方法
US20080142946A1 (en) * 2006-12-13 2008-06-19 Advanced Chip Engineering Technology Inc. Wafer level package with good cte performance
JP2009059771A (ja) * 2007-08-30 2009-03-19 Kyushu Institute Of Technology ウエハレベルチップサイズパッケージ及びその製造方法
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
KR101214746B1 (ko) * 2008-09-03 2012-12-21 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
US8406004B2 (en) * 2008-12-09 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
US8110926B2 (en) * 2009-01-30 2012-02-07 Broadcom Corporation Redistribution layer power grid
US8378383B2 (en) * 2009-03-25 2013-02-19 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US8691626B2 (en) * 2010-09-09 2014-04-08 Advanced Micro Devices, Inc. Semiconductor chip device with underfill
US8384225B2 (en) 2010-11-12 2013-02-26 Xilinx, Inc. Through silicon via with improved reliability
JP2013153122A (ja) * 2011-10-20 2013-08-08 Nitto Denko Corp 半導体装置の製造方法
US9748203B2 (en) 2011-12-15 2017-08-29 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8558395B2 (en) 2012-02-21 2013-10-15 Broadcom Corporation Organic interface substrate having interposer with through-semiconductor vias

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101159240A (zh) * 2006-10-02 2008-04-09 恩益禧电子股份有限公司 电子设备和制造电子设备的方法
US20100123239A1 (en) * 2008-11-17 2010-05-20 Shinko Electric Industries Co., Ltd. Semiconductor package and method of manufacturing the same
US20110042796A1 (en) * 2009-08-20 2011-02-24 Shu-Ming Chang Chip package and fabrication method thereof
CN102640283A (zh) * 2009-12-29 2012-08-15 英特尔公司 具有嵌入式管芯的半导体封装及其制造方法
CN102656686A (zh) * 2009-12-29 2012-09-05 英特尔公司 凹陷型嵌入式管芯无核封装
US20110316146A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Anisotropic Conductive Film Between Semiconductor Die and Build-Up Interconnect Structure
US20110316156A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
CN102299143A (zh) * 2010-06-25 2011-12-28 台湾积体电路制造股份有限公司 半导体元件
CN102403239A (zh) * 2010-09-13 2012-04-04 新科金朋有限公司 半导体器件及形成用于在Fo-WLCSP中安装半导体小片的引线上键合互连的方法
CN103119712A (zh) * 2010-09-24 2013-05-22 英特尔公司 使用在包括嵌入式管芯的内建非凹凸层衬底上的硅通孔的管芯堆叠,以及其形成工艺
CN102487020A (zh) * 2010-12-03 2012-06-06 新科金朋有限公司 形成引线上凸块互连的半导体器件和方法
CN102931173A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装
CN103066043A (zh) * 2011-10-20 2013-04-24 台湾积体电路制造股份有限公司 半导体封装件
CN103066050A (zh) * 2011-10-21 2013-04-24 台湾积体电路制造股份有限公司 具有银含量可控的焊料接合区域的半导体封装件
US20140015131A1 (en) * 2012-07-13 2014-01-16 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109494162A (zh) * 2017-09-11 2019-03-19 日月光半导体制造股份有限公司 多模件扇出型封装及工艺
US11152274B2 (en) 2017-09-11 2021-10-19 Advanced Semiconductor Engineering, Inc. Multi-moldings fan-out package and process
CN115298819A (zh) * 2020-03-23 2022-11-04 高通股份有限公司 包括衬底以及与衬底耦合的高密度互连集成器件的封装件
CN112420531A (zh) * 2020-11-27 2021-02-26 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
WO2022165854A1 (zh) * 2021-02-08 2022-08-11 广东省科学院半导体研究所 一种芯片互连封装结构及方法
US12112956B2 (en) 2021-02-08 2024-10-08 Institute of semiconductors, Guangdong Academy of Sciences Chip interconnection package structure and method

Also Published As

Publication number Publication date
WO2015134638A1 (en) 2015-09-11
US9230936B2 (en) 2016-01-05
US20150255416A1 (en) 2015-09-10
JP2017507495A (ja) 2017-03-16
EP3114707A1 (en) 2017-01-11

Similar Documents

Publication Publication Date Title
CN110060974B (zh) 包括重分布层上的堆叠管芯的集成器件
US9230936B2 (en) Integrated device comprising high density interconnects and redistribution layers
US9418877B2 (en) Integrated device comprising high density interconnects in inorganic layers and redistribution layers in organic layers
US9947642B2 (en) Package-on-Package (PoP) device comprising a gap controller between integrated circuit (IC) packages
CN106415832A (zh) 集成器件的重分布层(rdl)中的超环电感器
US9153560B2 (en) Package on package (PoP) integrated device comprising a redistribution layer
US20160141234A1 (en) Integrated device package comprising silicon bridge in photo imageable layer
US20160343646A1 (en) High aspect ratio interconnect for wafer level package (wlp) and integrated circuit (ic) package
CN105981166A (zh) 包括具有穿过封装层的侧势垒层的通孔的集成器件
CN107112310A (zh) 包括高性能封装间连接的层叠封装（pop）器件
CN106233458B (zh) 包括作为封装层中的通孔的导线的集成器件
CN108604585A (zh) 包括集成电路(ic)封装之间的柔性连接器的集成器件

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20161102