CN106068558A - 包括高密度互连和重分布层的集成器件 - Google Patents

包括高密度互连和重分布层的集成器件 Download PDF

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Publication number
CN106068558A
CN106068558A CN201580011603.4A CN201580011603A CN106068558A CN 106068558 A CN106068558 A CN 106068558A CN 201580011603 A CN201580011603 A CN 201580011603A CN 106068558 A CN106068558 A CN 106068558A
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China
Prior art keywords
die
interconnects
implementations
integrated device
redistribution
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Pending
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CN201580011603.4A
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English (en)
Chinese (zh)
Inventor
D·W·金
H·B·蔚
J·S·李
S·顾
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN106068558A publication Critical patent/CN106068558A/zh
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01Manufacture or treatment
    • H10W70/05Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/0198Manufacture or treatment batch processes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241Dispositions, e.g. layouts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251Materials
    • H10W72/252Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/9413Dispositions of bond pads on encapsulations
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/941Dispositions of bond pads
    • H10W72/9415Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/01Manufacture or treatment
    • H10W74/019Manufacture or treatment using temporary auxiliary substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/10Configurations of laterally-adjacent chips

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
CN201580011603.4A 2014-03-04 2015-03-04 包括高密度互连和重分布层的集成器件 Pending CN106068558A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/196,817 US9230936B2 (en) 2014-03-04 2014-03-04 Integrated device comprising high density interconnects and redistribution layers
US14/196,817 2014-03-04
PCT/US2015/018784 WO2015134638A1 (en) 2014-03-04 2015-03-04 Integrated device comprising high density interconnects and redistribution layers

Publications (1)

Publication Number Publication Date
CN106068558A true CN106068558A (zh) 2016-11-02

Family

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Family Applications (1)

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CN201580011603.4A Pending CN106068558A (zh) 2014-03-04 2015-03-04 包括高密度互连和重分布层的集成器件

Country Status (5)

Country Link
US (1) US9230936B2 (enExample)
EP (1) EP3114707A1 (enExample)
JP (1) JP2017507495A (enExample)
CN (1) CN106068558A (enExample)
WO (1) WO2015134638A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109494162A (zh) * 2017-09-11 2019-03-19 日月光半导体制造股份有限公司 多模件扇出型封装及工艺
CN112420531A (zh) * 2020-11-27 2021-02-26 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
WO2022165854A1 (zh) * 2021-02-08 2022-08-11 广东省科学院半导体研究所 一种芯片互连封装结构及方法
CN115298819A (zh) * 2020-03-23 2022-11-04 高通股份有限公司 包括衬底以及与衬底耦合的高密度互连集成器件的封装件

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2018009145A1 (en) * 2016-07-08 2018-01-11 Agency For Science, Technology And Research A semiconductor package and methods of forming the same
WO2018063263A1 (en) * 2016-09-29 2018-04-05 Intel Corporation Panel level packaging for multi-die products interconnected with very high density (vhd) interconnect layers
US10727185B2 (en) 2016-09-30 2020-07-28 Intel Corporation Multi-chip package with high density interconnects
US9799618B1 (en) * 2016-10-12 2017-10-24 International Business Machines Corporation Mixed UBM and mixed pitch on a single die
US10181449B1 (en) * 2017-09-28 2019-01-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure
KR102124892B1 (ko) * 2017-09-29 2020-06-22 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 팬-아웃 패키징 공정에서의 범프 정렬
US11217555B2 (en) * 2017-09-29 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Aligning bumps in fan-out packaging process
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
US10679946B2 (en) * 2018-04-10 2020-06-09 Wispry, Inc. Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates
US10665673B2 (en) 2018-06-28 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure with non-gated well tap cell
US11322450B2 (en) 2018-10-18 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package and method of forming the same
US11832391B2 (en) * 2020-09-30 2023-11-28 Qualcomm Incorporated Terminal connection routing and method the same
US11705420B2 (en) * 2020-10-29 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-bump connection to interconnect structure and manufacturing method thereof
US11869833B2 (en) * 2021-09-15 2024-01-09 Qualcomm Incorporated Package comprising a substrate with a via interconnect coupled to a trace interconnect and method of fabricating the same
CN118202460A (zh) * 2021-11-05 2024-06-14 美商艾德亚半导体接合科技有限公司 多沟道器件堆叠
US20240421095A1 (en) * 2023-06-19 2024-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof

Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101159240A (zh) * 2006-10-02 2008-04-09 恩益禧电子股份有限公司 电子设备和制造电子设备的方法
US20100123239A1 (en) * 2008-11-17 2010-05-20 Shinko Electric Industries Co., Ltd. Semiconductor package and method of manufacturing the same
US20110042796A1 (en) * 2009-08-20 2011-02-24 Shu-Ming Chang Chip package and fabrication method thereof
CN102299143A (zh) * 2010-06-25 2011-12-28 台湾积体电路制造股份有限公司 半导体元件
US20110316156A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
US20110316146A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Anisotropic Conductive Film Between Semiconductor Die and Build-Up Interconnect Structure
CN102403239A (zh) * 2010-09-13 2012-04-04 新科金朋有限公司 半导体器件及形成用于在Fo-WLCSP中安装半导体小片的引线上键合互连的方法
CN102487020A (zh) * 2010-12-03 2012-06-06 新科金朋有限公司 形成引线上凸块互连的半导体器件和方法
CN102640283A (zh) * 2009-12-29 2012-08-15 英特尔公司 具有嵌入式管芯的半导体封装及其制造方法
CN102656686A (zh) * 2009-12-29 2012-09-05 英特尔公司 凹陷型嵌入式管芯无核封装
CN102931173A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装
CN103066050A (zh) * 2011-10-21 2013-04-24 台湾积体电路制造股份有限公司 具有银含量可控的焊料接合区域的半导体封装件
CN103066043A (zh) * 2011-10-20 2013-04-24 台湾积体电路制造股份有限公司 半导体封装件
CN103119712A (zh) * 2010-09-24 2013-05-22 英特尔公司 使用在包括嵌入式管芯的内建非凹凸层衬底上的硅通孔的管芯堆叠,以及其形成工艺
US20140015131A1 (en) * 2012-07-13 2014-01-16 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5353498A (en) * 1993-02-08 1994-10-11 General Electric Company Method for fabricating an integrated circuit module
JP3728847B2 (ja) * 1997-02-04 2005-12-21 株式会社日立製作所 マルチチップモジュールおよびその製造方法
US20080142946A1 (en) * 2006-12-13 2008-06-19 Advanced Chip Engineering Technology Inc. Wafer level package with good cte performance
JP2009059771A (ja) * 2007-08-30 2009-03-19 Kyushu Institute Of Technology ウエハレベルチップサイズパッケージ及びその製造方法
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
KR101214746B1 (ko) * 2008-09-03 2012-12-21 삼성전기주식회사 웨이퍼 레벨 패키지 및 그 제조방법
US8406004B2 (en) * 2008-12-09 2013-03-26 Stats Chippac Ltd. Integrated circuit packaging system and method of manufacture thereof
US8110926B2 (en) * 2009-01-30 2012-02-07 Broadcom Corporation Redistribution layer power grid
US8378383B2 (en) * 2009-03-25 2013-02-19 Stats Chippac, Ltd. Semiconductor device and method of forming a shielding layer between stacked semiconductor die
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
US20110186960A1 (en) 2010-02-03 2011-08-04 Albert Wu Techniques and configurations for recessed semiconductor substrates
US8691626B2 (en) * 2010-09-09 2014-04-08 Advanced Micro Devices, Inc. Semiconductor chip device with underfill
US8384225B2 (en) 2010-11-12 2013-02-26 Xilinx, Inc. Through silicon via with improved reliability
JP2013153122A (ja) * 2011-10-20 2013-08-08 Nitto Denko Corp 半導体装置の製造方法
US9748203B2 (en) 2011-12-15 2017-08-29 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with conductive pillars and method of manufacture thereof
US8558395B2 (en) 2012-02-21 2013-10-15 Broadcom Corporation Organic interface substrate having interposer with through-semiconductor vias

Patent Citations (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101159240A (zh) * 2006-10-02 2008-04-09 恩益禧电子股份有限公司 电子设备和制造电子设备的方法
US20100123239A1 (en) * 2008-11-17 2010-05-20 Shinko Electric Industries Co., Ltd. Semiconductor package and method of manufacturing the same
US20110042796A1 (en) * 2009-08-20 2011-02-24 Shu-Ming Chang Chip package and fabrication method thereof
CN102640283A (zh) * 2009-12-29 2012-08-15 英特尔公司 具有嵌入式管芯的半导体封装及其制造方法
CN102656686A (zh) * 2009-12-29 2012-09-05 英特尔公司 凹陷型嵌入式管芯无核封装
US20110316156A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming RDL Along Sloped Side Surface of Semiconductor Die for Z-Direction Interconnect
US20110316146A1 (en) * 2010-06-24 2011-12-29 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Anisotropic Conductive Film Between Semiconductor Die and Build-Up Interconnect Structure
CN102299143A (zh) * 2010-06-25 2011-12-28 台湾积体电路制造股份有限公司 半导体元件
CN102403239A (zh) * 2010-09-13 2012-04-04 新科金朋有限公司 半导体器件及形成用于在Fo-WLCSP中安装半导体小片的引线上键合互连的方法
CN103119712A (zh) * 2010-09-24 2013-05-22 英特尔公司 使用在包括嵌入式管芯的内建非凹凸层衬底上的硅通孔的管芯堆叠,以及其形成工艺
CN102487020A (zh) * 2010-12-03 2012-06-06 新科金朋有限公司 形成引线上凸块互连的半导体器件和方法
CN102931173A (zh) * 2011-08-10 2013-02-13 台湾积体电路制造股份有限公司 多芯片晶圆级封装
CN103066043A (zh) * 2011-10-20 2013-04-24 台湾积体电路制造股份有限公司 半导体封装件
CN103066050A (zh) * 2011-10-21 2013-04-24 台湾积体电路制造股份有限公司 具有银含量可控的焊料接合区域的半导体封装件
US20140015131A1 (en) * 2012-07-13 2014-01-16 Intel Mobile Communications GmbH Stacked fan-out semiconductor chip

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109494162A (zh) * 2017-09-11 2019-03-19 日月光半导体制造股份有限公司 多模件扇出型封装及工艺
US11152274B2 (en) 2017-09-11 2021-10-19 Advanced Semiconductor Engineering, Inc. Multi-moldings fan-out package and process
CN115298819A (zh) * 2020-03-23 2022-11-04 高通股份有限公司 包括衬底以及与衬底耦合的高密度互连集成器件的封装件
CN112420531A (zh) * 2020-11-27 2021-02-26 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
WO2022165854A1 (zh) * 2021-02-08 2022-08-11 广东省科学院半导体研究所 一种芯片互连封装结构及方法
US12112956B2 (en) 2021-02-08 2024-10-08 Institute of semiconductors, Guangdong Academy of Sciences Chip interconnection package structure and method

Also Published As

Publication number Publication date
US20150255416A1 (en) 2015-09-10
WO2015134638A1 (en) 2015-09-11
EP3114707A1 (en) 2017-01-11
US9230936B2 (en) 2016-01-05
JP2017507495A (ja) 2017-03-16

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Application publication date: 20161102