JP2017507495A - 高密度インターコネクトおよび再分配層を備える集積デバイス - Google Patents

高密度インターコネクトおよび再分配層を備える集積デバイス Download PDF

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JP2017507495A
JP2017507495A JP2016555342A JP2016555342A JP2017507495A JP 2017507495 A JP2017507495 A JP 2017507495A JP 2016555342 A JP2016555342 A JP 2016555342A JP 2016555342 A JP2016555342 A JP 2016555342A JP 2017507495 A JP2017507495 A JP 2017507495A
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die
interconnects
redistribution
layer
integrated device
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JP2017507495A5 (enExample
Inventor
ドン・ウク・キム
ホン・ボク・ウィ
ジェ・シク・イ
シーチュン・グ
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クアルコム，インコーポレイテッド
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    • H10W70/09—
    • H10W70/093—
    • H10W70/60—
    • H10W70/614—
    • H10W72/0198—
    • H10W74/111—
    • H10W74/131—
    • H10W72/241—
    • H10W72/252—
    • H10W72/29—
    • H10W72/9413—
    • H10W72/9415—
    • H10W74/019—
    • H10W74/10—
    • H10W90/10—

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2016555342A 2014-03-04 2015-03-04 高密度インターコネクトおよび再分配層を備える集積デバイス Pending JP2017507495A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/196,817 US9230936B2 (en) 2014-03-04 2014-03-04 Integrated device comprising high density interconnects and redistribution layers
US14/196,817 2014-03-04
PCT/US2015/018784 WO2015134638A1 (en) 2014-03-04 2015-03-04 Integrated device comprising high density interconnects and redistribution layers

Publications (2)

Publication Number Publication Date
JP2017507495A true JP2017507495A (ja) 2017-03-16
JP2017507495A5 JP2017507495A5 (enExample) 2018-03-29

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JP2016555342A Pending JP2017507495A (ja) 2014-03-04 2015-03-04 高密度インターコネクトおよび再分配層を備える集積デバイス

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Country Link
US (1) US9230936B2 (enExample)
EP (1) EP3114707A1 (enExample)
JP (1) JP2017507495A (enExample)
CN (1) CN106068558A (enExample)
WO (1) WO2015134638A1 (enExample)

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US11217555B2 (en) * 2017-09-29 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Aligning bumps in fan-out packaging process
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US10867954B2 (en) 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
US10679946B2 (en) * 2018-04-10 2020-06-09 Wispry, Inc. Methods and devices for solderless integration of multiple semiconductor dies on flexible substrates
US10665673B2 (en) 2018-06-28 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure with non-gated well tap cell
US11322450B2 (en) 2018-10-18 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Chip package and method of forming the same
US11605594B2 (en) * 2020-03-23 2023-03-14 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate
US11832391B2 (en) * 2020-09-30 2023-11-28 Qualcomm Incorporated Terminal connection routing and method the same
US11705420B2 (en) * 2020-10-29 2023-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-bump connection to interconnect structure and manufacturing method thereof
CN112420531B (zh) * 2020-11-27 2021-11-30 上海易卜半导体有限公司 半导体封装方法、半导体组件以及包含其的电子设备
CN113169075B (zh) * 2021-02-08 2022-06-03 广东省科学院半导体研究所 一种芯片互连封装结构及方法
US11869833B2 (en) * 2021-09-15 2024-01-09 Qualcomm Incorporated Package comprising a substrate with a via interconnect coupled to a trace interconnect and method of fabricating the same
JP2024537478A (ja) * 2021-11-05 2024-10-10 アデイア セミコンダクター ボンディング テクノロジーズ インコーポレイテッド マルチチャンネル型デバイス積層化
US20240421095A1 (en) * 2023-06-19 2024-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and manufacturing method thereof

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Publication number Priority date Publication date Assignee Title
JPH077134A (ja) * 1993-02-08 1995-01-10 General Electric Co <Ge> 集積回路モジュール
JPH10223832A (ja) * 1997-02-04 1998-08-21 Hitachi Ltd マルチチップモジュールおよびその製造方法
JP2008091638A (ja) * 2006-10-02 2008-04-17 Nec Electronics Corp 電子装置およびその製造方法
JP2009059771A (ja) * 2007-08-30 2009-03-19 Kyushu Institute Of Technology ウエハレベルチップサイズパッケージ及びその製造方法
JP2012253396A (ja) * 2008-09-03 2012-12-20 Samsung Electro-Mechanics Co Ltd ウエハレベルパッケージ及びその製造方法
JP2010123592A (ja) * 2008-11-17 2010-06-03 Shinko Electric Ind Co Ltd 半導体パッケージ及びその製造方法
JP2013539910A (ja) * 2010-09-09 2013-10-28 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド アンダーフィル付き半導体チップデバイス
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Also Published As

Publication number Publication date
US9230936B2 (en) 2016-01-05
US20150255416A1 (en) 2015-09-10
WO2015134638A1 (en) 2015-09-11
CN106068558A (zh) 2016-11-02
EP3114707A1 (en) 2017-01-11

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