JP2016511552A5 - - Google Patents

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Publication number
JP2016511552A5
JP2016511552A5 JP2016501298A JP2016501298A JP2016511552A5 JP 2016511552 A5 JP2016511552 A5 JP 2016511552A5 JP 2016501298 A JP2016501298 A JP 2016501298A JP 2016501298 A JP2016501298 A JP 2016501298A JP 2016511552 A5 JP2016511552 A5 JP 2016511552A5
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JP
Japan
Prior art keywords
package
package substrate
die
interconnects
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2016501298A
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English (en)
Japanese (ja)
Other versions
JP6243509B2 (ja
JP2016511552A (ja
Filing date
Publication date
Priority claimed from US13/833,921 external-priority patent/US9484327B2/en
Application filed filed Critical
Publication of JP2016511552A publication Critical patent/JP2016511552A/ja
Publication of JP2016511552A5 publication Critical patent/JP2016511552A5/ja
Application granted granted Critical
Publication of JP6243509B2 publication Critical patent/JP6243509B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2016501298A 2013-03-15 2014-03-11 低減された高さのパッケージオンパッケージ構造 Expired - Fee Related JP6243509B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/833,921 2013-03-15
US13/833,921 US9484327B2 (en) 2013-03-15 2013-03-15 Package-on-package structure with reduced height
PCT/US2014/023626 WO2014150564A1 (en) 2013-03-15 2014-03-11 Package-on-package structure with reduced height

Publications (3)

Publication Number Publication Date
JP2016511552A JP2016511552A (ja) 2016-04-14
JP2016511552A5 true JP2016511552A5 (enExample) 2017-03-23
JP6243509B2 JP6243509B2 (ja) 2017-12-06

Family

ID=50543317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016501298A Expired - Fee Related JP6243509B2 (ja) 2013-03-15 2014-03-11 低減された高さのパッケージオンパッケージ構造

Country Status (6)

Country Link
US (1) US9484327B2 (enExample)
EP (1) EP2973700A1 (enExample)
JP (1) JP6243509B2 (enExample)
KR (1) KR20150132338A (enExample)
CN (1) CN105190883B (enExample)
WO (1) WO2014150564A1 (enExample)

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KR20150096949A (ko) * 2014-02-17 2015-08-26 삼성전자주식회사 반도체 패키지 및 그의 형성방법
US10453785B2 (en) 2014-08-07 2019-10-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming double-sided fan-out wafer level package
EP3198644A4 (en) 2014-09-26 2018-05-23 Intel Corporation Integrated circuit package having wire-bonded multi-die stack
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9601472B2 (en) * 2015-04-24 2017-03-21 Qualcomm Incorporated Package on package (POP) device comprising solder connections between integrated circuit device packages
US9679873B2 (en) * 2015-06-18 2017-06-13 Qualcomm Incorporated Low profile integrated circuit (IC) package comprising a plurality of dies
US9704825B2 (en) 2015-09-30 2017-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
US9806048B2 (en) * 2016-03-16 2017-10-31 Qualcomm Incorporated Planar fan-out wafer level packaging
US10121766B2 (en) 2016-06-30 2018-11-06 Micron Technology, Inc. Package-on-package semiconductor device assemblies including one or more windows and related methods and packages
CN106098676A (zh) * 2016-08-15 2016-11-09 黄卫东 多通道堆叠封装结构及封装方法
US20180053753A1 (en) * 2016-08-16 2018-02-22 Freescale Semiconductor, Inc. Stackable molded packages and methods of manufacture thereof
WO2018043129A1 (ja) * 2016-08-31 2018-03-08 株式会社村田製作所 回路モジュールおよびその製造方法
KR102504293B1 (ko) 2017-11-29 2023-02-27 삼성전자 주식회사 패키지 온 패키지 형태의 반도체 패키지
DE102019117844A1 (de) * 2018-09-27 2020-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte-schaltung-package und verfahren
KR102756186B1 (ko) * 2020-02-05 2025-01-17 삼성전자주식회사 반도체 패키지 및 패키지-온-패키지의 제조 방법
US11715699B2 (en) 2020-03-17 2023-08-01 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor devices and methods of manufacturing semiconductor devices
TWI891722B (zh) * 2020-03-17 2025-08-01 新加坡商安靠科技新加坡控股私人有限公司 半導體裝置和製造半導體裝置的方法
KR102877210B1 (ko) * 2020-06-22 2025-10-28 삼성전자주식회사 반도체 패키지
US11527518B2 (en) 2020-07-27 2022-12-13 Taiwan Semiconductor Manufacturing Co., Ltd. Heat dissipation in semiconductor packages and methods of forming same
WO2023089988A1 (ja) * 2021-11-22 2023-05-25 株式会社村田製作所 モジュール

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JP3273244B2 (ja) * 1998-04-14 2002-04-08 日本航空電子工業株式会社 高密度マルチチップモジュールおよびその製造方法
JP3838331B2 (ja) * 1999-05-14 2006-10-25 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
JP2006049569A (ja) * 2004-08-04 2006-02-16 Sharp Corp スタック型半導体装置パッケージおよびその製造方法
US7196427B2 (en) * 2005-04-18 2007-03-27 Freescale Semiconductor, Inc. Structure having an integrated circuit on another integrated circuit with an intervening bent adhesive element
US7528474B2 (en) 2005-05-31 2009-05-05 Stats Chippac Ltd. Stacked semiconductor package assembly having hollowed substrate
US7408254B1 (en) * 2005-08-26 2008-08-05 Amkor Technology Inc Stack land grid array package and method for manufacturing the same
JP2007123705A (ja) 2005-10-31 2007-05-17 Elpida Memory Inc 積層型半導体装置及びその製造方法
JP2007194516A (ja) * 2006-01-23 2007-08-02 Matsushita Electric Ind Co Ltd 複合配線基板およびその製造方法、ならびに電子部品の実装体および製造方法
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US7635914B2 (en) 2007-05-17 2009-12-22 Texas Instruments Incorporated Multi layer low cost cavity substrate fabrication for pop packages
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US7687899B1 (en) * 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
US8247893B2 (en) 2007-12-27 2012-08-21 Stats Chippac Ltd. Mountable integrated circuit package system with intra-stack encapsulation
KR101486420B1 (ko) 2008-07-25 2015-01-26 삼성전자주식회사 칩 패키지, 이를 이용한 적층형 패키지 및 그 제조 방법
US20100327419A1 (en) 2009-06-26 2010-12-30 Sriram Muthukumar Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
JP2011052292A (ja) * 2009-09-03 2011-03-17 Shingijutsu Kenkyusho:Kk アルミニウム合金物品、アルミニウム合金部材およびその製造方法
US8541872B2 (en) 2010-06-02 2013-09-24 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
US8669651B2 (en) 2010-07-26 2014-03-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structures with reduced bump bridging
US8384227B2 (en) 2010-11-16 2013-02-26 Stats Chippac, Ltd. Semiconductor device and method of forming interposer frame electrically connected to embedded semiconductor die
US8409917B2 (en) * 2011-03-22 2013-04-02 Stats Chippac Ltd. Integrated circuit packaging system with an interposer substrate and method of manufacture thereof

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