JP2017538280A5 - - Google Patents

Download PDF

Info

Publication number
JP2017538280A5
JP2017538280A5 JP2017513769A JP2017513769A JP2017538280A5 JP 2017538280 A5 JP2017538280 A5 JP 2017538280A5 JP 2017513769 A JP2017513769 A JP 2017513769A JP 2017513769 A JP2017513769 A JP 2017513769A JP 2017538280 A5 JP2017538280 A5 JP 2017538280A5
Authority
JP
Japan
Prior art keywords
solder
opening
forming
pad
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2017513769A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017538280A (ja
Filing date
Publication date
Priority claimed from US14/529,859 external-priority patent/US10431533B2/en
Application filed filed Critical
Publication of JP2017538280A publication Critical patent/JP2017538280A/ja
Publication of JP2017538280A5 publication Critical patent/JP2017538280A5/ja
Priority to JP2021138724A priority Critical patent/JP7301919B2/ja
Pending legal-status Critical Current

Links

JP2017513769A 2014-10-31 2015-10-07 制約されたはんだ相互接続パッドを備える回路基板 Pending JP2017538280A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2021138724A JP7301919B2 (ja) 2014-10-31 2021-08-27 制約されたはんだ相互接続パッドを備える回路基板

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/529,859 US10431533B2 (en) 2014-10-31 2014-10-31 Circuit board with constrained solder interconnect pads
US14/529,859 2014-10-31
PCT/CA2015/051015 WO2016065460A1 (en) 2014-10-31 2015-10-07 Circuit board with constrained solder interconnect pads

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2021138724A Division JP7301919B2 (ja) 2014-10-31 2021-08-27 制約されたはんだ相互接続パッドを備える回路基板

Publications (2)

Publication Number Publication Date
JP2017538280A JP2017538280A (ja) 2017-12-21
JP2017538280A5 true JP2017538280A5 (enExample) 2018-11-08

Family

ID=55853496

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2017513769A Pending JP2017538280A (ja) 2014-10-31 2015-10-07 制約されたはんだ相互接続パッドを備える回路基板
JP2021138724A Active JP7301919B2 (ja) 2014-10-31 2021-08-27 制約されたはんだ相互接続パッドを備える回路基板

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2021138724A Active JP7301919B2 (ja) 2014-10-31 2021-08-27 制約されたはんだ相互接続パッドを備える回路基板

Country Status (6)

Country Link
US (1) US10431533B2 (enExample)
EP (1) EP3213609A4 (enExample)
JP (2) JP2017538280A (enExample)
KR (1) KR102310979B1 (enExample)
CN (1) CN106717138A (enExample)
WO (1) WO2016065460A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate
US11804440B2 (en) * 2021-01-28 2023-10-31 Globalfoundries U.S. Inc. Chip module with robust in-package interconnects
KR20240001780A (ko) 2022-06-27 2024-01-04 삼성전자주식회사 반도체 패키지

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5471090A (en) 1993-03-08 1995-11-28 International Business Machines Corporation Electronic structures having a joining geometry providing reduced capacitive loading
EP0759231B1 (de) 1994-05-02 1998-12-23 SIEMENS MATSUSHITA COMPONENTS GmbH & CO. KG Verkapselung für elektronische bauelemente
US5796589A (en) 1995-12-20 1998-08-18 Intel Corporation Ball grid array integrated circuit package that has vias located within the solder pads of a package
DE19548046C2 (de) * 1995-12-21 1998-01-15 Siemens Matsushita Components Verfahren zur Herstellung von für eine Flip-Chip-Montage geeigneten Kontakten von elektrischen Bauelementen
US5759910A (en) 1996-12-23 1998-06-02 Motorola, Inc. Process for fabricating a solder bump for a flip chip integrated circuit
US5859474A (en) 1997-04-23 1999-01-12 Lsi Logic Corporation Reflow ball grid array assembly
KR100345035B1 (ko) * 1999-11-06 2002-07-24 한국과학기술원 무전해 도금법을 이용한 고속구리배선 칩 접속용 범프 및 ｕｂｍ 형성방법
US6774474B1 (en) 1999-11-10 2004-08-10 International Business Machines Corporation Partially captured oriented interconnections for BGA packages and a method of forming the interconnections
JP2001223460A (ja) 2000-02-08 2001-08-17 Fujitsu Ltd 実装回路基板及びその製造方法
JP2002026500A (ja) * 2000-07-05 2002-01-25 Ngk Spark Plug Co Ltd 配線基板
KR100426897B1 (ko) * 2001-08-21 2004-04-30 주식회사 네패스 솔더 터미널 및 그 제조방법
US7335995B2 (en) 2001-10-09 2008-02-26 Tessera, Inc. Microelectronic assembly having array including passive elements and interconnects
US6888255B2 (en) 2003-05-30 2005-05-03 Texas Instruments Incorporated Built-up bump pad structure and method for same
TW572361U (en) 2003-06-03 2004-01-11 Via Tech Inc Flip-chip package carrier
US7367489B2 (en) 2003-07-01 2008-05-06 Chippac, Inc. Method and apparatus for flip chip attachment by post collapse re-melt and re-solidification of bumps
JP2005109187A (ja) * 2003-09-30 2005-04-21 Tdk Corp フリップチップ実装回路基板およびその製造方法ならびに集積回路装置
US20050189622A1 (en) 2004-03-01 2005-09-01 Tessera, Inc. Packaged acoustic and electromagnetic transducer chips
TWI231165B (en) * 2004-06-30 2005-04-11 Phoenix Prec Technology Corp Method for fabricating electrical connection structure of circuit board
KR100556351B1 (ko) * 2004-07-27 2006-03-03 동부아남반도체 주식회사 반도체 소자의 금속 패드 및 금속 패드 본딩 방법
US7339275B2 (en) 2004-11-22 2008-03-04 Freescale Semiconductor, Inc. Multi-chips semiconductor device assemblies and methods for fabricating the same
JP2007234919A (ja) * 2006-03-02 2007-09-13 Cmk Corp プリント配線板とその製造方法
US8124520B2 (en) 2006-07-10 2012-02-28 Stats Chippac Ltd. Integrated circuit mount system with solder mask pad
JP5193503B2 (ja) * 2007-06-04 2013-05-08 新光電気工業株式会社 貫通電極付き基板及びその製造方法
US7670939B2 (en) 2008-05-12 2010-03-02 Ati Technologies Ulc Semiconductor chip bump connection apparatus and method
KR101111930B1 (ko) 2008-09-30 2012-02-14 이비덴 가부시키가이샤 다층 프린트 배선판, 및 다층 프린트 배선판의 제조 방법
KR101022942B1 (ko) 2008-11-12 2011-03-16 삼성전기주식회사 흐름 방지용 댐을 구비한 인쇄회로기판 및 그 제조방법
US20110110061A1 (en) * 2009-11-12 2011-05-12 Leung Andrew Kw Circuit Board with Offset Via
JP2012079759A (ja) * 2010-09-30 2012-04-19 Sumitomo Bakelite Co Ltd 回路基板、回路基板の製造方法および半導体装置
KR101332049B1 (ko) * 2012-01-13 2013-11-22 삼성전기주식회사 인쇄회로기판의 제조방법
JP5913063B2 (ja) * 2012-11-27 2016-04-27 日本特殊陶業株式会社 配線基板

Similar Documents

Publication Publication Date Title
CN103996630B (zh) 封装半导体器件和封装器件及方法
CN103177977B (zh) 通过选择性处理暴露封装件中的连接件
US10163662B2 (en) Fabrication method of semiconductor package
US9607963B2 (en) Semiconductor device and fabrication method thereof
TWI446508B (zh) 無核心式封裝基板及其製法
JP2016213238A5 (enExample)
TW201342556A (zh) 半導體裝置的封裝體及半導體裝置的封裝方法
CN104037140B (zh) 半导体装置
TWI613785B (zh) 三維集成電路封裝及其製造方法
JP2015149325A5 (enExample)
CN102270590A (zh) 晶圆级封装结构及封装方法
CN103050466B (zh) 半导体封装件及其制法
CN104867909A (zh) 用于有源装置的嵌入式管芯再分布层
US8138594B2 (en) Semiconductor device and manufacturing method of a semiconductor device
JP2017538280A5 (enExample)
TW201521164A (zh) 封裝堆疊結構及其製法
TWI652779B (zh) 半導體封裝及其製造方法
JP2018507556A5 (enExample)
CN104517936B (zh) 封装结构
TW201336369A (zh) 線路板製作方法及線路板
JP2011249564A5 (enExample)
CN104851865A (zh) 覆晶式封装基板、覆晶式封装件及其制法
TWI548049B (zh) 半導體結構及其製法
TWM537303U (zh) ３ｄ多晶片模組封裝結構（二）
TWI637471B (zh) 封裝結構及其製作方法