CN104851865A - 覆晶式封装基板、覆晶式封装件及其制法 - Google Patents

覆晶式封装基板、覆晶式封装件及其制法 Download PDF

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CN104851865A
CN104851865A CN201410089589.7A CN201410089589A CN104851865A CN 104851865 A CN104851865 A CN 104851865A CN 201410089589 A CN201410089589 A CN 201410089589A CN 104851865 A CN104851865 A CN 104851865A
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flip
metal level
chip type
type package
protective layer
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林长甫
姚进财
庄旻锦
陈柏华
黄富堂
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
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    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
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    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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Abstract

一种覆晶式封装基板、覆晶式封装件及其制法，该覆晶式封装基板包括基板本体、多个电性连接垫、绝缘保护层与金属层，该电性连接垫形成于该基板本体的一表面上，该绝缘保护层形成于该基板本体的该表面上与该电性连接垫上，且具有多个对应外露部分各该电性连接垫的开孔，该金属层形成于该开孔中的电性连接垫上，该金属层的顶面的最低点低于该绝缘保护层的顶面，且该金属层的厚度与该绝缘保护层的厚度的比值大于或等于1/4并小于1。本发明能解决现有的焊料桥接与短路的问题。

Description

覆晶式封装基板、覆晶式封装件及其制法
技术领域
本发明涉及一种封装基板、封装件及其制法，尤指一种覆晶式封装基板、覆晶式封装件及其制法。
背景技术
图1所示者，其为现有的覆晶式封装件的剖视图，如图所示，该基板本体10的一表面上形成有多个电性连接垫11，于该基板本体10的该表面上与该电性连接垫11上覆盖有绝缘保护层12，且该绝缘保护层12具有多个对应外露部分各该电性连接垫11的开孔120，该绝缘保护层12的厚度约为20至30微米，接着，藉由多个焊球13将一半导体晶片14接置于该基板本体10上。
然而，在回焊该焊球时，该焊球的体积会膨胀约30至50%，使得部分该焊球钻入该绝缘保护层与电性连接垫之间或该绝缘保护层与基板本体之间，造成焊料挤出（solder extrusion），在相邻该电性连接垫间的间距较小的情况下，容易导致桥接（bridge）而短路（short），进而降低产品良率。
于另一种现有的覆晶式封装件（未图示）中，其通过于该电性连接垫上形成顶面高于该绝缘保护层的铜柱，并藉由该铜柱的顶端电性连接半导体晶片；然而，此种覆晶式封装件于遭受到侧向外力时，该铜柱容易与该电性连接垫分离，同样会降低产品良率。
因此，如何避免上述现有技术中的种种问题，实为目前业界所急需解决的课题。
发明内容
有鉴于上述现有技术的缺失，本发明提供一种覆晶式封装基板、覆晶式封装件及其制法，能解决焊料桥接与短路的问题。
本发明的覆晶式封装基板包括：基板本体；多个电性连接垫，其形成于该基板本体的一表面上；绝缘保护层，其形成于该基板本体的该表面上与该电性连接垫上，且具有多个对应外露部分各该电性连接垫的开孔；以及金属层，其形成于该开孔中的电性连接垫上，该金属层的顶面的最低点低于该绝缘保护层的顶面，且该金属层的厚度与该绝缘保护层的厚度的比值大于或等于1/4并小于1。
本发明还提供一种覆晶式封装基板的制法，包括：于基板本体的一表面上形成多个电性连接垫；于该基板本体的该表面上与该电性连接垫上形成绝缘保护层，该绝缘保护层并具有多个对应外露部分各该电性连接垫的开孔；以及于该开孔中的电性连接垫上形成金属层，该金属层的顶面的最低点低于该绝缘保护层的顶面，且该金属层的厚度与该绝缘保护层的厚度的比值大于或等于1/4并小于1。
本发明又提供一种覆晶式封装件，包括：基板本体；多个电性连接垫，其形成于该基板本体的一表面上；绝缘保护层，其形成于该基板本体的该表面上与该电性连接垫上，且具有多个对应外露部分各该电性连接垫的开孔；金属层，其形成于该开孔中的电性连接垫上，该金属层的顶面的最低点低于该绝缘保护层的顶面，且该金属层的厚度与该绝缘保护层的厚度的比值大于或等于1/4并小于1；以及半导体晶片，其藉由多个焊球电性连接该金属层。
本发明再提供一种覆晶式封装件的制法，包括：提供一覆晶式封装基板，其包括：基板本体；多个电性连接垫，其形成于该基板本体的一表面上；绝缘保护层，其形成于该基板本体的该表面上与该电性连接垫上，且具有多个对应外露部分各该电性连接垫的开孔；及金属层，其形成于该开孔中的电性连接垫上，该金属层的顶面的最低点低于该绝缘保护层的顶面，且该金属层的厚度与该绝缘保护层的厚度的比值大于或等于1/4并小于1；以及藉由多个焊球将半导体晶片电性连接该金属层。
由上可知，本发明能减少焊料的体积，进而减少焊料的膨胀体积；此外，本发明使得相邻两焊球间的路径加长，故即使发生焊料挤出现象也不容易导致桥接与短路。
附图说明
图1所示者为现有的覆晶式封装件的剖视图。
图2A至图2C所示者为本发明的覆晶式封装基板的不同实施例的剖视图，其中，图2A’为图2A的其中一种制作过程的剖视图。
图3所示者为本发明的覆晶式封装件的剖视图。
主要组件符号说明
10、20    基板本体
11、21    电性连接垫
12、22    绝缘保护层
120、220  开孔
13、31    焊球
14、30    半导体晶片
23        金属层
23’      金属块
230       凹槽。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用以配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用以限定本发明可实施的限定条件，故不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的用语也仅为便于叙述的明了，而非用以限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2C所示者，为本发明的覆晶式封装基板的不同实施例的剖视图。如图所示，本发明的覆晶式封装基板包括：基板本体20；多个电性连接垫21，其形成于该基板本体20的一表面上；绝缘保护层22，其形成于该基板本体20的该表面上与该电性连接垫21上，且具有多个对应外露部分各该电性连接垫21的开孔220；以及金属层23，其形成于该开孔220中的电性连接垫21上，该金属层23的顶面的最低点低于该绝缘保护层22的顶面。
又本发明的覆晶式封装基板的制法包括：于基板本体20的一表面上形成多个电性连接垫21；于该基板本体20的该表面上与该电性连接垫21上形成绝缘保护层22，该绝缘保护层22并具有多个对应外露部分各该电性连接垫21的开孔220；以及藉由涂布或电镀方式于该开孔220中的电性连接垫21上形成金属层23，该金属层23的顶面的最低点低于该绝缘保护层22的顶面。
于前述的制法中，形成该金属层23的步骤可直接电镀形成至预定厚度的该金属层23，于另一实施例中，形成该金属层23的步骤可包括：于该开孔220中的电性连接垫21上形成金属块23’（如图2A’所示）；以及移除部分该金属块23’的顶部，以构成该金属层23，且移除部分该金属块23’的方式为蚀刻。
于前述的覆晶式封装基板及其制法中，形成该金属层23的材质例如为铜，其厚度为4至20微米，且该金属层23的厚度与该绝缘保护层22的厚度的比值大于或等于1/4并小于1，较佳范围为1/3至3/4。
前述的封装基板及其制法中，该金属层23的厚度为该金属层23顶面最低点至该电性连接垫21顶面的距离，该金属层23的厚度与该绝缘保护层22的厚度的比值为该金属层23的厚度除以该绝缘保护层22的厚度所得到的商。该金属层23的厚度与该绝缘保护层22的厚度的比值等于1/4为具有功效的最小值；若该金属层23的厚度与该绝缘保护层22的厚度的比值等于1时，则该金属层23无凸出该绝缘保护层22的侧壁供焊球包覆固定，该绝缘保护层22内也无空间可容置焊球，使得焊球容易向外溢流，所以该金属层23的厚度与该绝缘保护层22的厚度的比值等于1为上限，较佳范围为1/3至3/4，可提供足够厚度的该金属层23，且该绝缘保护层22内也有容置空间。
如图2B与图2C所示，该金属层23延伸形成于该开孔220的孔壁，且金属层23的顶面还具有一凹槽230，该金属层23的顶面的最高点齐平于该绝缘保护层22的顶面，该凹槽230呈碗状，如图2B所示，或者，该凹槽230呈顶宽底窄，且该凹槽230具有平坦的底面与平坦的斜面，如图2C所示。
于本发明的覆晶式封装基板及其制法中，还包括表面处理层（未图示），其形成于该金属层23上，且形成该表面处理层的材质为镍/金（Ni/Au）、镍/钯/金（Ni/Pd/Au）或有机保焊剂（OSP）。
图3所示者，为本发明的覆晶式封装件的剖视图。如图所示，本发明的覆晶式封装件包括：基板本体20；多个电性连接垫21，其形成于该基板本体20的一表面上；绝缘保护层22，其形成于该基板本体20的该表面上与该电性连接垫21上，且具有多个对应外露部分各该电性连接垫21的开孔220；金属层23，其形成于该开孔220中的电性连接垫21上，该金属层23的顶面的最低点低于该绝缘保护层22的顶面；以及半导体晶片30，其藉由多个焊球31电性连接该金属层23。
又本发明的覆晶式封装件的制法先提供一本发明的覆晶式封装基板，再藉由多个该焊球31将该半导体晶片30电性连接该金属层23。
于本发明的覆晶式封装件的制法中，若形成该表面处理层的材质为镍/金（Ni/Au）或镍/钯/金（Ni/Pd/Au），则于回焊该焊球31时，该镍/金（Ni/Au）或镍/钯/金（Ni/Pd/Au）会熔解而熔入该焊球31中；若形成该表面处理层的材质为有机保焊剂（OSP），则需先移除该有机保焊剂（OSP），才接置该焊球31与半导体晶片30。
综上所述，相较于现有技术，由于本发明通过于电性连接垫上形成金属层，所以该金属层能取代部分的焊料，而能减少焊料的体积，进而减少焊料的膨胀体积；此外，增加的该金属层与绝缘保护层间的接触面积将使得相邻两焊球间的路径加长，故即使发生焊料挤出现象也不容易导致桥接与短路，如图3所示，因此能提高产品良率；此外，因为焊料润湿（solder wetting）的表面低于绝缘保护层的顶面，所以也可分散应力，并减少金属层与电性连接垫分离的情形。
上述实施例仅用以例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如权利要求书所列。

Claims (38)

1.一种覆晶式封装基板，包括：
基板本体；
多个电性连接垫，其形成于该基板本体的一表面上；
绝缘保护层，其形成于该基板本体的该表面上与该电性连接垫上，且具有多个对应外露部分各该电性连接垫的开孔；以及
金属层，其形成于该开孔中的电性连接垫上，该金属层的顶面的最低点低于该绝缘保护层的顶面，且该金属层的厚度与该绝缘保护层的厚度的比值大于或等于1/4并小于1。
2.如权利要求1所述的覆晶式封装基板，其特征在于，该金属层的厚度与该绝缘保护层的厚度的比值为1/3至3/4。
3.如权利要求1所述的覆晶式封装基板，其特征在于，该金属层的顶面还具有一凹槽。
4.如权利要求3所述的覆晶式封装基板，其特征在于，该凹槽呈碗状。
5.如权利要求3所述的覆晶式封装基板，其特征在于，该凹槽呈顶宽底窄，且该凹槽具有平坦的底面与平坦的斜面。
6.如权利要求1所述的覆晶式封装基板，其特征在于，该金属层延伸形成于该开孔的孔壁。
7.如权利要求6所述的覆晶式封装基板，其特征在于，该金属层的顶面的最高点齐平于该绝缘保护层的顶面。
8.如权利要求1所述的覆晶式封装基板，其特征在于，该基板还包括表面处理层，其形成于该金属层上。
9.如权利要求1所述的覆晶式封装基板，其特征在于，形成该金属层的材质为铜。
10.一种覆晶式封装基板的制法，包括：
于基板本体的一表面上形成多个电性连接垫；
于该基板本体的该表面上与该电性连接垫上形成绝缘保护层，该绝缘保护层并具有多个对应外露部分各该电性连接垫的开孔；以及
于该开孔中的电性连接垫上形成金属层，该金属层的顶面的最低点低于该绝缘保护层的顶面，且该金属层的厚度与该绝缘保护层的厚度的比值大于或等于1/4并小于1。
11.如权利要求10所述的覆晶式封装基板的制法，其特征在于，形成该金属层的步骤为直接电镀形成至预定厚度的该金属层。
12.如权利要求10所述的覆晶式封装基板的制法，其特征在于，形成该金属层的步骤包括：
于该开孔中的电性连接垫上形成金属块；以及
移除部分该金属块的顶部，以构成该金属层。
13.如权利要求12所述的覆晶式封装基板的制法，其特征在于，移除部分该金属块的方式为蚀刻。
14.如权利要求10所述的覆晶式封装基板的制法，其特征在于，该金属层的厚度与该绝缘保护层的厚度的比值为1/3至3/4。
15.如权利要求10所述的覆晶式封装基板的制法，其特征在于，该金属层的顶面还具有一凹槽。
16.如权利要求15所述的覆晶式封装基板的制法，其特征在于，该凹槽呈碗状。
17.如权利要求15所述的覆晶式封装基板的制法，其特征在于，该凹槽呈顶宽底窄，且该凹槽具有平坦的底面与平坦的斜面。
18.如权利要求10所述的覆晶式封装基板的制法，其特征在于，该金属层延伸形成于该开孔的孔壁。
19.如权利要求18所述的覆晶式封装基板的制法，其特征在于，该金属层的顶面的最高点齐平于该绝缘保护层的顶面。
20.如权利要求10所述的覆晶式封装基板的制法，其特征在于，该制法还包括于该金属层上形成表面处理层。
21.如权利要求10所述的覆晶式封装基板的制法，其特征在于，形成该金属层的材质为铜。
22.一种覆晶式封装件，包括：
基板本体；
多个电性连接垫，其形成于该基板本体的一表面上；
绝缘保护层，其形成于该基板本体的该表面上与该电性连接垫上，且具有多个对应外露部分各该电性连接垫的开孔；
金属层，其形成于该开孔中的电性连接垫上，该金属层的顶面的最低点低于该绝缘保护层的顶面，且该金属层的厚度与该绝缘保护层的厚度的比值大于或等于1/4并小于1；以及
半导体晶片，其藉由多个焊球电性连接该金属层。
23.如权利要求22所述的覆晶式封装件，其特征在于，该金属层的厚度与该绝缘保护层的厚度的比值为1/3至3/4。
24.如权利要求22所述的覆晶式封装件，其特征在于，该金属层的顶面还具有一凹槽。
25.如权利要求24所述的覆晶式封装件，其特征在于，该凹槽呈碗状。
26.如权利要求24所述的覆晶式封装件，其特征在于，该凹槽呈顶宽底窄，且该凹槽具有平坦的底面与平坦的斜面。
27.如权利要求22所述的覆晶式封装基板的制法，其特征在于，该金属层延伸形成于该开孔的孔壁。
28.如权利要求27所述的覆晶式封装件，其特征在于，该金属层的顶面的最高点齐平于该绝缘保护层的顶面。
29.如权利要求22所述的覆晶式封装件，其特征在于，形成该金属层的材质为铜。
30.一种覆晶式封装件的制法，包括：
提供一覆晶式封装基板，其包括：
基板本体；
多个电性连接垫，其形成于该基板本体的一表面上；
绝缘保护层，其形成于该基板本体的该表面上与该电性连接垫上，且具有多个对应外露部分各该电性连接垫的开孔；及
金属层，其形成于该开孔中的电性连接垫上，该金属层的顶面的最低点低于该绝缘保护层的顶面，且该金属层的厚度与该绝缘保护层的厚度的比值大于或等于1/4并小于1；以及
藉由多个焊球将半导体晶片电性连接该金属层。
31.如权利要求30所述的覆晶式封装件的制法，其特征在于，该金属层的厚度与该绝缘保护层的厚度的比值为1/3至3/4。
32.如权利要求30所述的覆晶式封装件的制法，其特征在于，该金属层的顶面还具有一凹槽。
33.如权利要求32所述的覆晶式封装件的制法，其特征在于，该凹槽呈碗状。
34.如权利要求32所述的覆晶式封装件的制法，其特征在于，该凹槽呈顶宽底窄，且该凹槽具有平坦的底面与平坦的斜面。
35.如权利要求30所述的覆晶式封装件的制法，其特征在于，该金属层延伸形成于该开孔的孔壁。
36.如权利要求35所述的覆晶式封装件的制法，其特征在于，该金属层的顶面的最高点齐平于该绝缘保护层的顶面。
37.如权利要求30所述的覆晶式封装件的制法，其特征在于，于将该半导体晶片电性连接该金属层之前，还包括于该金属层上形成表面处理层。
38.如权利要求30所述的覆晶式封装件的制法，其特征在于，形成该金属层的材质为铜。
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Application publication date: 20150819