CN105374798A - 中介板及其制法 - Google Patents

中介板及其制法 Download PDF

Info

Publication number
CN105374798A
CN105374798A CN201410460338.5A CN201410460338A CN105374798A CN 105374798 A CN105374798 A CN 105374798A CN 201410460338 A CN201410460338 A CN 201410460338A CN 105374798 A CN105374798 A CN 105374798A
Authority
CN
China
Prior art keywords
conductive
electric contact
contact mat
plate body
perforate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201410460338.5A
Other languages
English (en)
Inventor
张文璟
林健民
吴柏毅
卢俊宏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN105374798A publication Critical patent/CN105374798A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/145—Organic substrates, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

一种中介板及其制法，先绝缘保护层于板体上，且该绝缘保护层具有多个开孔，再形成电性接触垫于各该开孔中，所以藉由先形成该绝缘保护层，再制作该电性接触垫，因而无需进行湿蚀刻制程，使该电性接触垫不会有底切现象。

Description

中介板及其制法
技术领域
本发明涉及一种中介板，尤指一种用于半导体封装件的中介板及其制法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐迈向多功能、高性能的趋势。目前应用于晶片封装领域的技术，例如晶片尺寸构装(ChipScalePackage,CSP)、晶片直接贴附封装(DirectChipAttached,DCA)或多晶片模组封装(Multi－ChipModule,MCM)等覆晶型态的封装模组、或将晶片立体堆迭化整合为三维积体电路(3DIC)晶片堆迭技术等。
图1为现有3D晶片堆迭的半导体封装件的制法的剖面示意图。如图1所示，提供一硅中介板(ThroughSiliconinterposer,TSI)1，该硅中介板1具有具有相对的置晶侧10b与转接侧10a、及连通该置晶侧10b与转接侧10a的多个导电硅穿孔(Through-siliconvia,TSV)100，且该置晶侧10b上具有一线路重布结构(Redistributionlayer,RDL)11。将间距较小的半导体晶片6的电极垫60藉由多个焊锡凸块61电性结合至该线路重布结构11上，再以底胶62包覆该些焊锡凸块61，且于该导电硅穿孔100上藉由多个如凸块的导电元件18电性结合间距较大的封装基板7的焊垫70，之后形成封装胶体8于该封装基板7上，以包覆该半导体晶片6。
图1A至图1G为现有硅中介板1的转接侧10a的制法的剖面示意图。
如图1A所示，提供一具有相对的转接侧10a与置晶侧10b的硅板体10，且该硅板体10具有连通该转接侧10a与置晶侧10b的多个导电硅穿孔100，又该硅板体10的置晶侧10b上具有一电性连接该导电硅穿孔100的线路重布结构11，该转接侧10a具有一钝化层12。
如图1B所示，形成一导电层14(俗称晶种层)于该钝化层12与各该导电硅穿孔100上。
如图1C所示，利用阻层(图略)图案化电镀形成电性接触垫16上于各该导电硅穿孔100上，之后移除该阻层。目前一般硅中介板1的线宽/线高可为3μm以下(如图1C’所示的电性接触垫16的厚度d)，而晶种层的厚度一般约在1μm以下(如图1C’所示的导电层14的厚度t)。
如图1D所示，湿蚀刻移除该阻层下的导电层14，且该电性接触垫16电性连接该导电硅穿孔100。
如图1E所示，形成一绝缘保护层13于该钝化层12与各该电性接触垫16上，且该绝缘保护层13具有多个开孔130，以令各该电性接触垫16对应外露于各该开孔130。
如图1F所示，形成另一导电层14’于该绝缘保护层13与该电性接触垫16上，再利用另一阻层17图案化电镀形成如焊锡材料的导电元件18于各该电性接触垫16上。
如图1G所示，移除该阻层17及其下的导电层14’。
惟，前述现有硅中介板1的制法中，于图1C的制程的阻层下的导电层14尚未去除，所以当移除该阻层下的导电层14时，湿蚀刻会等向性蚀刻，即使蚀刻湿蚀刻所使用的药液会有选择性蚀刻，但该电性接触垫16下的导电层14亦会受蚀，而产生底切现象(如图1C’所示的导电层14的底切宽度r)，造成该电性接触垫16的底部过细而无法立设于该导电硅穿孔100上。
此外，于进行湿蚀刻制程时，该电性接触垫16也会部分受蚀，致使该电性接触垫16无法达到原先的预设宽度L(如图1C’所示)，因而会产生电性问题。
因此，如何克服上述现有技术的种种问题，实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的种种缺失，本发明提供一种中介板及其制法，无需进行湿蚀刻制程，使该电性接触垫不会有底切现象。
本发明的中介板，包括：板体，其具有相对的第一侧与第二侧、及连通该第一侧与第二侧的多个导电穿孔；绝缘保护层，其形成于该板体的第一侧上，且该绝缘保护层具有多个开孔，以令各该导电穿孔对应外露于各该开孔；多个电性接触垫，各设于各该开孔中，且电性连接该导电穿孔；以及导电层，其设于该开孔与该电性接触垫之间。
本发明还提供一种中介板的制法，其包括：提供一具有相对的第一侧与第二侧的板体，且该板体具有连通该第一侧与第二侧的多个导电穿孔；形成绝缘保护层于该板体的第一侧上，且该绝缘保护层具有多个开孔，以令各该导电穿孔对应外露于各该开孔；以及形成电性接触垫于各该开孔中，且该电性接触垫电性连接该导电穿孔。
前述的制法中，该电性接触垫为以电镀方式形成者。
前述的中介板及其制法中，该板体为半导体板体。
前述的中介板及其制法中，该板体的第一侧具有钝化层。
前述的中介板及其制法中，该板体的第二侧上具有线路结构，且该导电穿孔电性连接该线路结构。
前述的中介板及其制法中，该电性接触垫的表面齐平该绝缘保护层的表面。
前述的中介板及其制法中，该电性接触垫的制程包括：形成导电层于该绝缘保护层上与各该开孔中；形成导电材于该绝缘保护层上的导电层上与各该开孔中；移除该绝缘保护层上的导电层及其上的导电材，且保留各该开孔中的导电材以作为该电性接触垫。因此，该导电层设于该导电穿孔与该电性接触垫之间、及该开孔与该电性接触垫之间。
前述的中介板及其制法中，还包括形成导电元件于各该电性接触垫上。
由上可知，本发明的中介板及其制法，藉由先形成该绝缘保护层于该板体的第一侧上，以形成电性接触垫于各该开孔中，所以相较于现有技术，本发明于制作该电性接触垫时，无需移除图案化用的阻层及无需进行湿蚀刻制程，因而可减少材料等使用成本，并能简化制程，以提高产量。
此外，因无需进行湿蚀刻制程，所以该电性接触垫与该导电层不会产生底切现象，因而可避免现有技术所产生的问题。
附图说明
图1为现有硅中介板的剖面示意图；
图1A至图1G为现有硅中介板的制法的剖面示意图；其中，图1C’为图1C的局部放大图；以及
图2A至图2G为本发明的中介板的制法的剖面示意图。
符号说明
1硅中介板
10,20板体
10a转接侧
10b置晶侧
100导电硅穿孔
11线路重布结构
12,22钝化层
13,23绝缘保护层
130,230开孔
14,14’,24,24’导电层
16,26电性接触垫
17,27阻层
18,28导电元件
2中介板
20a第一侧
20b第二侧
200导电穿孔
21线路结构
210介电层
211线路层
23a,23b表面
25导电材
6半导体晶片
60电极垫
61焊锡凸块
62底胶
7封装基板
70焊垫
8封装胶体
d,t厚度
L预设宽度
r底切宽度。
具体实施方式
以下藉由特定的具体实施例说明本发明的实施方式，本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供本领域技术人员的了解与阅读，并非用于限定本发明可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本发明所能产生的功效及所能达成的目的下，均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如“上”、“第一”、“第二”及“一”等用语，也仅为便于叙述的明了，而非用于限定本发明可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当也视为本发明可实施的范畴。
图2A至图2G为本发明的中介板2的制法的第一实施例的剖面示意图。
如图2A所示，提供一具有相对的第一侧20a(可视为转接侧)与第二侧20b(可视为置晶侧)的板体20，且该板体20为半导体板体，其具有连通该第一侧20a与第二侧20b的多个导电穿孔200。
于本实施例中，该板体20为含硅板体，例如，硅晶圆或玻璃基板，且藉由线路重布层(Redistributionlayer,RDL)制程，于该板体20的第二侧20b上已制作出一电性连接该导电穿孔200的线路结构21，其中，该线路结构21具有至少一介电层210与设于该介电层210上并电性连接该导电穿孔200的线路层211。
此外，该板体20的第一侧20a具有一钝化层22，且该钝化层22为氧化层(如二氧化硅)或氮化层(如氮化硅)。
如图2B所示，形成一绝缘保护层23于该板体20的第一侧20a的钝化层22上，且该绝缘保护层23具有多个开孔230，以令各该导电穿孔200对应外露于各该开孔230。
于本实施例中，该绝缘保护层23为氧化层(如二氧化硅)或氮化层(如氮化硅层)。
如图2C所示，形成一导电层24于该绝缘保护层23上与各该开孔230中。接着，形成如铜的导电材25于该绝缘保护层23上的导电层24上与各该开孔230中。
于本实施例中，进行线路重布层(Redistributionlayer,RDL)制程，利用该导电层24进行电镀步骤，以形成该导电材25。
如图2D所示，进行化学机械研磨(Chemical-MechanicalPolishing，简称CMP)制程，移除该绝缘保护层23上的导电层24及其上的导电材25，且保留各该开孔230中的导电材25，以形成多个电性接触垫26于各该开孔230中，且该电性接触垫26电性连接该导电穿孔200。
于本实施例中，该电性接触垫26的表面26a齐平该绝缘保护层23的表面23a。
如图2E所示，形成另一导电层24’于该绝缘保护层23与该电性接触垫26上，再利用阻层27图案化电镀形成如焊锡材料的导电元件28于各该电性接触垫26上。
如图2F所示，移除该阻层27及其下的导电层24’。
如图2G所示，回焊各该导电元件28。
本发明的制法中，利用先形成该绝缘保护层23于该板体20的第一侧20a上，以于该板体20的第一侧20a上全面电镀该导电材25，再移除多余的导电材25及其下的导电层24，所以相较于现有技术，本发明于制作该电性接触垫26时，无需移除图案化用的阻层及无需进行湿蚀刻制程，因而可减少材料等使用成本，并能简化制程，以提高产量。
此外，因无需进行湿蚀刻制程，所以该电性接触垫26与该导电层24不会有底切现象，因而无现有技术所产生的问题。
本发明提供一种中介板2，包括：一板体20、一绝缘保护层23、多个电性接触垫26以及一导电层24。
所述的板体20具有相对的第一侧20a与第二侧20b、及连通该第一侧20a与第二侧20b的多个导电穿孔200，且该板体20的第二侧20b上具有线路结构21，又该导电穿孔200电性连接该线路结构21。
所述的绝缘保护层23形成于该板体20的第一侧20a上，且该绝缘保护层23具有多个开孔230，以令各该导电穿孔200对应外露于各该开孔230。
所述的电性接触垫26设于各该开孔230中，且电性连接该导电穿孔200。
所述的导电层24设于该开孔230与该电性接触垫26之间、及该导电穿孔200与该电性接触垫26之间。
于一实施例中，该板体20为半导体板体。
于一实施例中，该板体20的第一侧20a具有一钝化层22。
于一实施例中，该电性接触垫26的表面26a齐平该绝缘保护层23的表面23a。
于一实施例中，所述的中介板2还包括多个导电元件28，其设于该电性接触垫26上。
综上所述，本发明的中介板及其制法，其藉由先形成该绝缘保护层，再制作该电性接触垫，所以无需进行湿蚀刻制程，因而可减少材料等使用成本，并能简化制程以提高产量，且不会有底切现象，以提高制作良率。
上述实施例仅用于例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修改。因此本发明的权利保护范围，应如后述权利要求书所列。

Claims (18)

1.一种中介板，其包括：
板体，其具有相对的第一侧与第二侧、及连通该第一侧与第二侧的多个导电穿孔；
绝缘保护层，其形成于该板体的第一侧上，且该绝缘保护层具有多个开孔，以令各该导电穿孔对应外露于各该开孔；
多个电性接触垫，各设于各该开孔中，且电性连接该导电穿孔；以及
导电层，其设于该开孔与该电性接触垫之间。
2.如权利要求1所述的中介板，其特征为，该板体为半导体板体。
3.如权利要求1所述的中介板，其特征为，该板体的第一侧具有至少一钝化层。
4.如权利要求1所述的中介板，其特征为，该板体的第二侧上具有线路结构。
5.如权利要求4所述的中介板，其特征为，该导电穿孔电性连接该线路结构。
6.如权利要求1所述的中介板，其特征为，该电性接触垫的表面齐平该绝缘保护层的表面。
7.如权利要求1所述的中介板，其特征为，该导电层还设于该导电穿孔与该电性接触垫之间。
8.如权利要求1所述的中介板，其特征为，该中介板还包括导电元件，其设于该电性接触垫上。
9.一种中介板的制法，其包括：
提供一具有相对的第一侧与第二侧的板体，且该板体具有连通该第一侧与第二侧的多个导电穿孔；
形成绝缘保护层于该板体的第一侧上，且该绝缘保护层具有多个开孔，以令各该导电穿孔对应外露于各该开孔；以及
形成电性接触垫于各该开孔中，且令各该电性接触垫电性连接对应的该导电穿孔。
10.如权利要求9所述的中介板的制法，其特征为，该板体为半导体板体。
11.如权利要求9所述的中介板的制法，其特征为，该板体的第一侧具有至少一钝化层。
12.如权利要求9所述的中介板的制法，其特征为，该板体的第二侧上具有线路结构。
13.如权利要求12所述的中介板的制法，其特征为，该导电穿孔电性连接该线路结构。
14.如权利要求9所述的中介板的制法，其特征为，该电性接触垫的表面齐平该绝缘保护层的表面。
15.如权利要求9所述的中介板的制法，其特征为，该电性接触垫以电镀方式形成者。
16.如权利要求9所述的中介板的制法，其特征为，该电性接触垫的制程包括：
形成导电层于该绝缘保护层上与各该开孔中；
形成导电材于该绝缘保护层上的导电层上与各该开孔中；
移除该绝缘保护层上的导电层及其上的导电材，且保留各该开孔中的导电材以作为该电性接触垫。
17.如权利要求16所述的中介板的制法，其特征为，该导电层设于该导电穿孔与该电性接触垫之间、及该开孔与该电性接触垫之间。
18.如权利要求9所述的中介板的制法，其特征为，该制法还包括形成导电元件于各该电性接触垫上。
CN201410460338.5A 2014-08-13 2014-09-11 中介板及其制法 Pending CN105374798A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW103127721 2014-08-13
TW103127721A TWI566354B (zh) 2014-08-13 2014-08-13 中介板及其製法

Publications (1)

Publication Number Publication Date
CN105374798A true CN105374798A (zh) 2016-03-02

Family

ID=55303209

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410460338.5A Pending CN105374798A (zh) 2014-08-13 2014-09-11 中介板及其制法

Country Status (3)

Country Link
US (1) US20160050753A1 (zh)
CN (1) CN105374798A (zh)
TW (1) TWI566354B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10687419B2 (en) * 2017-06-13 2020-06-16 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090166869A1 (en) * 2007-12-27 2009-07-02 Dongbu Hitek Co., Ltd. Semiconductor device and method of forming metal interconnection layer thereof
US20120305916A1 (en) * 2011-06-03 2012-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer Test Structures and Methods
CN103890939A (zh) * 2011-10-28 2014-06-25 英特尔公司 包括与穿硅过孔组合的细间距单镶嵌后侧金属再分布线的3d互连结构

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5824599A (en) * 1996-01-16 1998-10-20 Cornell Research Foundation, Inc. Protected encapsulation of catalytic layer for electroless copper interconnect
US5969422A (en) * 1997-05-15 1999-10-19 Advanced Micro Devices, Inc. Plated copper interconnect structure
US6610596B1 (en) * 1999-09-15 2003-08-26 Samsung Electronics Co., Ltd. Method of forming metal interconnection using plating and semiconductor device manufactured by the method
TWI303864B (en) * 2004-10-26 2008-12-01 Sanyo Electric Co Semiconductor device and method for making the same
US8836146B2 (en) * 2006-03-02 2014-09-16 Qualcomm Incorporated Chip package and method for fabricating the same
US8420520B2 (en) * 2006-05-18 2013-04-16 Megica Corporation Non-cyanide gold electroplating for fine-line gold traces and gold pads
JP2008141088A (ja) * 2006-12-05 2008-06-19 Nec Electronics Corp 半導体装置の製造方法
KR100833194B1 (ko) * 2006-12-19 2008-05-28 삼성전자주식회사 반도체 칩의 배선층이 기판에 직접 연결된 반도체 패키지및 그 제조방법
TWI408434B (zh) * 2007-10-05 2013-09-11 Hon Hai Prec Ind Co Ltd 鏡頭模組之組裝方法
US7709956B2 (en) * 2008-09-15 2010-05-04 National Semiconductor Corporation Copper-topped interconnect structure that has thin and thick copper traces and method of forming the copper-topped interconnect structure
JP5693961B2 (ja) * 2008-09-18 2015-04-01 国立大学法人 東京大学 半導体装置の製造方法
JP2010157690A (ja) * 2008-12-29 2010-07-15 Ibiden Co Ltd 電子部品実装用基板及び電子部品実装用基板の製造方法
US8198174B2 (en) * 2009-08-05 2012-06-12 International Business Machines Corporation Air channel interconnects for 3-D integration
JP5590869B2 (ja) * 2009-12-07 2014-09-17 新光電気工業株式会社 配線基板及びその製造方法並びに半導体パッケージ
US8837872B2 (en) * 2010-12-30 2014-09-16 Qualcomm Incorporated Waveguide structures for signal and/or power transmission in a semiconductor device
TWI543307B (zh) * 2012-09-27 2016-07-21 欣興電子股份有限公司 封裝載板與晶片封裝結構
TWI544599B (zh) * 2012-10-30 2016-08-01 矽品精密工業股份有限公司 封裝結構之製法
TWI499020B (zh) * 2012-11-28 2015-09-01 矽品精密工業股份有限公司 半導體基板之製法
WO2014209404A1 (en) * 2013-06-29 2014-12-31 Intel Corporation Interconnect structure comprising fine pitch backside metal redistribution lines combined with vias
US9070676B2 (en) * 2013-10-09 2015-06-30 Invensas Corporation Bowl-shaped solder structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090166869A1 (en) * 2007-12-27 2009-07-02 Dongbu Hitek Co., Ltd. Semiconductor device and method of forming metal interconnection layer thereof
US20120305916A1 (en) * 2011-06-03 2012-12-06 Taiwan Semiconductor Manufacturing Company, Ltd. Interposer Test Structures and Methods
CN103890939A (zh) * 2011-10-28 2014-06-25 英特尔公司 包括与穿硅过孔组合的细间距单镶嵌后侧金属再分布线的3d互连结构

Also Published As

Publication number Publication date
TW201606968A (zh) 2016-02-16
TWI566354B (zh) 2017-01-11
US20160050753A1 (en) 2016-02-18

Similar Documents

Publication Publication Date Title
KR102495911B1 (ko) 반도체 패키지
CN102163596B (zh) 集成电路元件及其形成方法
KR101107858B1 (ko) 반도체 기판을 위한 도전 필러 구조 및 그 제조 방법
CN103208482B (zh) 通孔组件模块及其形成方法
CN106935563B (zh) 电子封装件及其制法与基板结构
KR20160130820A (ko) 기판의 웰에 근접하여 기판 내에 배치되는 열 비아
JP2012253392A (ja) モールド再構成ウェハーを利用したスタックパッケージ及びその製造方法
CN105470235A (zh) 中介板及其制法
CN105374693A (zh) 半导体封装件及其形成方法
US20230335540A1 (en) Semiconductor package and method of fabricating the same
TW201532221A (zh) 半導體元件及其製造方法
CN103390600A (zh) 半导体封装件及其制法
CN106206509B (zh) 电子封装件及其制法与基板结构
TW201205769A (en) Device and method for forming the same
CN203085525U (zh) 可用于堆叠的集成电路
CN103794569A (zh) 封装结构及其制法
CN104347528A (zh) 半导体封装件及其制法
CN105097760A (zh) 半导体封装件及其制法与承载结构
US8896089B2 (en) Interposers for semiconductor devices and methods of manufacture thereof
CN105702658A (zh) 半导体封装件及其制法
TWI715131B (zh) 三維積體電路電源網與其形成方法
CN108074905A (zh) 电子装置及其制法与基板结构
CN108735684B (zh) 多晶片半导体封装体及垂直堆叠的半导体晶片和封装方法
KR101013556B1 (ko) 스택 패키지의 제조방법
US20050258536A1 (en) Chip heat sink device and method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20160302

WD01 Invention patent application deemed withdrawn after publication