JP2017538280A - 制約されたはんだ相互接続パッドを備える回路基板 - Google Patents
制約されたはんだ相互接続パッドを備える回路基板 Download PDFInfo
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- JP2017538280A JP2017538280A JP2017513769A JP2017513769A JP2017538280A JP 2017538280 A JP2017538280 A JP 2017538280A JP 2017513769 A JP2017513769 A JP 2017513769A JP 2017513769 A JP2017513769 A JP 2017513769A JP 2017538280 A JP2017538280 A JP 2017538280A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Geometry (AREA)
Abstract
Description
Claims (20)
- 側壁を有する第1の開口(220)を含むはんだマスク(75)を回路基板(20)に形成するステップと、
はんだ相互接続パッド(65)を前記第1の開口に形成するステップであって、前記側壁は、前記はんだ相互接続パッドの横方向の範囲を設定する、ステップと、
を含む、製造方法。 - 前記第1の開口を形成し、前記第1の開口に金属を配置して、前記はんだ相互接続パッドを形成する、請求項1の製造方法。
- 下層の導体パッド(120)を露出させる第2の開口(263)を前記回路基板の相互接続層(85)に形成するステップと、前記第1の開口が前記第2の開口と整列するように前記はんだマスクを形成するステップと、を含む、請求項2の製造方法。
- 前記第2の開口に導電ビア(140)を形成し、前記導電ビア上に前記はんだ相互接続パッドを形成するステップを含む、請求項3の製造方法。
- 前記はんだ相互接続パッドを形成した後に、前記はんだマスク及び前記第1の開口を、前記はんだ相互接続パッドに接触させることなく形成し、前記はんだ相互接続パッドと、前記はんだ相互接続パッドと前記側壁との間と、に金属を追加する、請求項1の製造方法。
- はんだバンプ(55)を前記はんだ相互接続パッドに結合するステップを含む、請求項1の製造方法。
- 半導体チップ(15)前記回路基板に結合するステップを含む、請求項1の製造方法。
- コンピュータ可読媒体に記憶された命令を用いて前記はんだマスク及び前記はんだ相互接続パッドを形成するステップを含む、請求項1の製造方法。
- 側壁を有する第1の開口(220)を含むはんだマスク(75)を半導体チップパッケージ基板(20)に形成するステップと、
はんだ相互接続パッド(65)を前記第1の開口に形成するステップであって、前記側壁は、前記はんだ相互接続パッドの横方向の範囲を設定する、ステップと、
を含む、製造方法。 - 前記第1の開口を形成し、前記第1の開口に金属を配置して、前記はんだ相互接続パッドを形成する、請求項9の製造方法。
- 下層の導体パッド(120)を露出させる第2の開口(263)を前記半導体チップパッケージ基板の相互接続層(85)に形成するステップと、前記第1の開口が前記第2の開口と整列するように前記はんだマスクを形成するステップと、を含む、請求項10の製造方法。
- 前記第2の開口に導電ビア(140)を形成し、前記導電ビア上に前記はんだ相互接続パッドを形成するステップを含む、請求項11の製造方法。
- 前記はんだ相互接続パッドを形成した後に、前記はんだマスク及び前記第1の開口を、前記はんだ相互接続パッドに接触させることなく形成し、前記はんだ相互接続パッドと、前記はんだ相互接続パッドと前記側壁との間と、に金属を追加する、請求項9の製造方法。
- 半導体チップ(15)を前記半導体チップパッケージ基板に結合するステップを含む、請求項9の製造方法。
- 複数のはんだボール(30)を前記半導体チップパッケージ基板に結合するステップを含む、請求項9の製造方法。
- 回路基板(20)であって、
側壁を有する第1の開口(220)を含む、前記回路基板のはんだマスク(75)と、
前記第1の開口のはんだ相互接続パッド(65)であって、前記側壁は、前記はんだ相互接続パッドの横方向の範囲を設定する、はんだ相互接続パッドと、
を備える、回路基板(20)。 - はんだバンプ(55)を前記はんだ相互接続パッドに結合することを含む、請求項16の回路基板。
- 前記回路基板に結合された半導体チップ(15)を備える、請求項16の回路基板。
- 前記はんだ相互接続パッドは上面(225)を含み、前記はんだマスクは前記上面と実質的に接触していない、請求項16の回路基板。
- 前記回路基板は半導体チップパッケージ基板を備える、請求項16の回路基板。
Priority Applications (1)
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JP2021138724A JP7301919B2 (ja) | 2014-10-31 | 2021-08-27 | 制約されたはんだ相互接続パッドを備える回路基板 |
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US14/529,859 | 2014-10-31 | ||
US14/529,859 US10431533B2 (en) | 2014-10-31 | 2014-10-31 | Circuit board with constrained solder interconnect pads |
PCT/CA2015/051015 WO2016065460A1 (en) | 2014-10-31 | 2015-10-07 | Circuit board with constrained solder interconnect pads |
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JP2021138724A Division JP7301919B2 (ja) | 2014-10-31 | 2021-08-27 | 制約されたはんだ相互接続パッドを備える回路基板 |
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JP2017538280A true JP2017538280A (ja) | 2017-12-21 |
JP2017538280A5 JP2017538280A5 (ja) | 2018-11-08 |
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JP2021138724A Active JP7301919B2 (ja) | 2014-10-31 | 2021-08-27 | 制約されたはんだ相互接続パッドを備える回路基板 |
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Country | Link |
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US (1) | US10431533B2 (ja) |
EP (1) | EP3213609A4 (ja) |
JP (2) | JP2017538280A (ja) |
KR (1) | KR102310979B1 (ja) |
CN (1) | CN106717138A (ja) |
WO (1) | WO2016065460A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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US11640934B2 (en) * | 2018-03-30 | 2023-05-02 | Intel Corporation | Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate |
US11804440B2 (en) * | 2021-01-28 | 2023-10-31 | Globalfoundries U.S. Inc. | Chip module with robust in-package interconnects |
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JP2014107371A (ja) * | 2012-11-27 | 2014-06-09 | Ngk Spark Plug Co Ltd | 配線基板 |
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-
2014
- 2014-10-31 US US14/529,859 patent/US10431533B2/en active Active
-
2015
- 2015-10-07 KR KR1020177007459A patent/KR102310979B1/ko active IP Right Grant
- 2015-10-07 WO PCT/CA2015/051015 patent/WO2016065460A1/en active Application Filing
- 2015-10-07 EP EP15854911.3A patent/EP3213609A4/en not_active Ceased
- 2015-10-07 JP JP2017513769A patent/JP2017538280A/ja active Pending
- 2015-10-07 CN CN201580048951.9A patent/CN106717138A/zh active Pending
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2021
- 2021-08-27 JP JP2021138724A patent/JP7301919B2/ja active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2005109187A (ja) * | 2003-09-30 | 2005-04-21 | Tdk Corp | フリップチップ実装回路基板およびその製造方法ならびに集積回路装置 |
JP2008300782A (ja) * | 2007-06-04 | 2008-12-11 | Shinko Electric Ind Co Ltd | 貫通電極付き基板の製造方法 |
JP2013511137A (ja) * | 2009-11-12 | 2013-03-28 | エーティーアイ・テクノロジーズ・ユーエルシー | オフセットされたビアを伴う回路板 |
JP2012079759A (ja) * | 2010-09-30 | 2012-04-19 | Sumitomo Bakelite Co Ltd | 回路基板、回路基板の製造方法および半導体装置 |
JP2014107371A (ja) * | 2012-11-27 | 2014-06-09 | Ngk Spark Plug Co Ltd | 配線基板 |
Also Published As
Publication number | Publication date |
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WO2016065460A1 (en) | 2016-05-06 |
CN106717138A (zh) | 2017-05-24 |
EP3213609A4 (en) | 2018-07-04 |
US20160126171A1 (en) | 2016-05-05 |
KR102310979B1 (ko) | 2021-10-08 |
JP2021185619A (ja) | 2021-12-09 |
US10431533B2 (en) | 2019-10-01 |
JP7301919B2 (ja) | 2023-07-03 |
EP3213609A1 (en) | 2017-09-06 |
KR20170078597A (ko) | 2017-07-07 |
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