JP2018507556A5 - - Google Patents

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Publication number
JP2018507556A5
JP2018507556A5 JP2017543343A JP2017543343A JP2018507556A5 JP 2018507556 A5 JP2018507556 A5 JP 2018507556A5 JP 2017543343 A JP2017543343 A JP 2017543343A JP 2017543343 A JP2017543343 A JP 2017543343A JP 2018507556 A5 JP2018507556 A5 JP 2018507556A5
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JP
Japan
Prior art keywords
substrate
conductive
dielectric
conductive posts
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017543343A
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English (en)
Japanese (ja)
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JP6789228B2 (ja
JP2018507556A (ja
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Publication date
Priority claimed from US14/859,318 external-priority patent/US9768108B2/en
Application filed filed Critical
Publication of JP2018507556A publication Critical patent/JP2018507556A/ja
Publication of JP2018507556A5 publication Critical patent/JP2018507556A5/ja
Application granted granted Critical
Publication of JP6789228B2 publication Critical patent/JP6789228B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2017543343A 2015-02-20 2016-02-18 集積回路パッケージ用の導電性ポスト保護 Active JP6789228B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562118886P 2015-02-20 2015-02-20
US62/118,886 2015-02-20
US14/859,318 2015-09-20
US14/859,318 US9768108B2 (en) 2015-02-20 2015-09-20 Conductive post protection for integrated circuit packages
PCT/US2016/018504 WO2016134165A1 (en) 2015-02-20 2016-02-18 Conductive post protection for integrated circuit packages

Publications (3)

Publication Number Publication Date
JP2018507556A JP2018507556A (ja) 2018-03-15
JP2018507556A5 true JP2018507556A5 (enExample) 2019-03-07
JP6789228B2 JP6789228B2 (ja) 2020-11-25

Family

ID=55442905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017543343A Active JP6789228B2 (ja) 2015-02-20 2016-02-18 集積回路パッケージ用の導電性ポスト保護

Country Status (8)

Country Link
US (1) US9768108B2 (enExample)
EP (1) EP3259776A1 (enExample)
JP (1) JP6789228B2 (enExample)
KR (1) KR102469282B1 (enExample)
CN (1) CN107251217B (enExample)
BR (1) BR112017017746A2 (enExample)
SG (1) SG11201705672XA (enExample)
WO (1) WO2016134165A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102397905B1 (ko) 2017-12-27 2022-05-13 삼성전자주식회사 인터포저 기판 및 반도체 패키지
US11791276B2 (en) * 2021-04-08 2023-10-17 Qualcomm Incorporated Package comprising passive component between substrates for improved power distribution network (PDN) performance
WO2023135720A1 (ja) * 2022-01-14 2023-07-20 キヤノン株式会社 モジュールおよび機器
US20250323136A1 (en) * 2024-04-12 2025-10-16 Qualcomm Incorporated Integrated circuit (ic) package including two substrates and vertical interconnects coupling the two substrates, the vertical interconnects comprising a metal ball and metal pin combination to address an increased distance between substrates

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JP2000208698A (ja) * 1999-01-18 2000-07-28 Toshiba Corp 半導体装置
JP2003347501A (ja) * 2002-05-23 2003-12-05 Hitachi Cable Ltd 半導体モジュール及びそれに用いる配線板、ならびに半導体モジュールの製造方法及び配線板の製造方法
JP3973624B2 (ja) * 2003-12-24 2007-09-12 富士通株式会社 高周波デバイス
JP4396839B2 (ja) * 2004-08-11 2010-01-13 日本電気株式会社 キャビティ構造プリント配線板とその製造方法及び実装構造
JP4551321B2 (ja) * 2005-07-21 2010-09-29 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP2007053235A (ja) * 2005-08-18 2007-03-01 Matsushita Electric Ind Co Ltd 基台及び半導体デバイス
JP2007123524A (ja) * 2005-10-27 2007-05-17 Shinko Electric Ind Co Ltd 電子部品内蔵基板
US7632708B2 (en) 2005-12-27 2009-12-15 Tessera, Inc. Microelectronic component with photo-imageable substrate
JP2007194436A (ja) * 2006-01-19 2007-08-02 Elpida Memory Inc 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法
JP2009099750A (ja) * 2007-10-17 2009-05-07 Powertech Technology Inc 半導体パッケージ
JP5185062B2 (ja) * 2008-10-21 2013-04-17 パナソニック株式会社 積層型半導体装置及び電子機器
US8623753B1 (en) * 2009-05-28 2014-01-07 Amkor Technology, Inc. Stackable protruding via package and method
JP2011095705A (ja) * 2009-09-30 2011-05-12 Fujifilm Corp 感光性組成物、感光性ソルダーレジスト組成物及び感光性ソルダーレジストフィルム、並びに、永久パターン、その形成方法及びプリント基板
US8169065B2 (en) * 2009-12-22 2012-05-01 Epic Technologies, Inc. Stackable circuit structures and methods of fabrication thereof
US8531021B2 (en) 2011-01-27 2013-09-10 Unimicron Technology Corporation Package stack device and fabrication method thereof
US8476770B2 (en) 2011-07-07 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and methods for forming through vias
US8637992B2 (en) 2011-11-30 2014-01-28 Invensas Corporation Flip chip package for DRAM with two underfill materials
US9362143B2 (en) 2012-05-14 2016-06-07 Micron Technology, Inc. Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages
CN103632988B (zh) * 2012-08-28 2016-10-19 宏启胜精密电子(秦皇岛)有限公司 层叠封装结构及其制作方法
CN103681365B (zh) * 2012-08-31 2016-08-10 宏启胜精密电子(秦皇岛)有限公司 层叠封装结构及其制作方法
CN103681359A (zh) * 2012-09-19 2014-03-26 宏启胜精密电子(秦皇岛)有限公司 层叠封装结构及其制作方法
US9368438B2 (en) 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
US8946901B2 (en) 2013-01-22 2015-02-03 Invensas Corporation Microelectronic package and method of manufacture thereof
US9378982B2 (en) 2013-01-31 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package
CN104051389B (zh) * 2013-03-12 2018-05-15 台湾积体电路制造股份有限公司 具有焊盘连接件上通孔的叠层封装件
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias

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