JP2018507556A - 集積回路パッケージ用の導電性ポスト保護 - Google Patents
集積回路パッケージ用の導電性ポスト保護 Download PDFInfo
- Publication number
- JP2018507556A JP2018507556A JP2017543343A JP2017543343A JP2018507556A JP 2018507556 A JP2018507556 A JP 2018507556A JP 2017543343 A JP2017543343 A JP 2017543343A JP 2017543343 A JP2017543343 A JP 2017543343A JP 2018507556 A JP2018507556 A JP 2018507556A
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- substrate
- conductive
- dielectric
- integrated circuit
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- 239000000758 substrate Substances 0.000 claims abstract description 203
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052802 copper Inorganic materials 0.000 claims abstract description 41
- 239000010949 copper Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims description 37
- 229910000679 solder Inorganic materials 0.000 claims description 33
- 239000002184 metal Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 238000007747 plating Methods 0.000 claims description 4
- 230000001681 protective effect Effects 0.000 abstract description 8
- 230000008569 process Effects 0.000 description 27
- 239000011248 coating agent Substances 0.000 description 20
- 238000000576 coating method Methods 0.000 description 20
- 239000000463 material Substances 0.000 description 15
- 239000011162 core material Substances 0.000 description 13
- 238000004519 manufacturing process Methods 0.000 description 12
- 239000004593 Epoxy Substances 0.000 description 3
- 230000009471 action Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007730 finishing process Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004925 Acrylic resin Substances 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
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- H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Combinations Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
本特許出願は、本明細書の譲受人に譲渡され、参照により本明細書に明示的に組み込まれる、2015年2月20日に出願された「COPPER POST PROTECTION FOR INTEGRATED CIRCUIT PACKAGES」という名称の仮出願第62/118,886号の優先権を主張するものである。
102 はんだレジスト
104 基板またはインターポーザ構造体
106a 導電性コンタクト
106b 導電性コンタクト
106c 導電性コンタクト
106d 導電性コンタクト
108a 導電性ポスト
108b 導電性ポスト
108c 導電性ポスト
108d 導電性ポスト
110 誘電体
112 領域、内部空間
202a 導電性パッド
202b 導電性パッド
202c 導電性パッド
202d 導電性パッド
302 第1の基板/インターポーザ組立体、底部基板/インターポーザ組立体
304 集積回路ダイ
306 第2の基板/インターポーザ組立体、上部基板/インターポーザ組立体
308a 導電性ポスト
308b 導電性ポスト
308c 導電性ポスト
308d 導電性ポスト
310a 導電性コンタクト
310b 導電性コンタクト
310c 導電性コンタクト
310d 導電性コンタクト
312 保護誘電体
314a はんだボール
314b はんだボール
314c はんだボール
314d はんだボール
316a 導電性コンタクト
316b 導電性コンタクト
316c 導電性コンタクト
316d 導電性コンタクト
402 底部基板/インターポーザ組立体
404 集積回路ダイ
406 上部基板/インターポーザ組立体
408a 導電性ポスト
408b 導電性ポスト
408c 導電性ポスト
408d 導電性ポスト
410a 導電性コンタクト
410b 導電性コンタクト
410c 導電性コンタクト
410d 導電性コンタクト
412 保護誘電体
414a はんだボール
414b はんだボール
414c はんだボール
414d はんだボール
416a 導電性コンタクト
416b 導電性コンタクト
416c 導電性コンタクト
416d 導電性コンタクト
418 内部空間
502 底部基板/インターポーザ組立体
504 集積回路ダイ
506 上部基板/インターポーザ組立体
508a 第1の複数の導電性ポスト
508b 第1の複数の導電性ポスト
508c 第1の複数の導電性ポスト
508d 第1の複数の導電性ポスト
510a 導電性コンタクト
510b 導電性コンタクト
510c 導電性コンタクト
510d 導電性コンタクト
512a 第2の複数の導電性ポスト
512b 第2の複数の導電性ポスト
512c 第2の複数の導電性ポスト
512d 第2の複数の導電性ポスト
514a 導電性コンタクト
514b 導電性コンタクト
514c 導電性コンタクト
514d 導電性コンタクト
516 誘電体
518 誘電体
520a はんだボール
520b はんだボール
520c はんだボール
520d はんだボール
522 内部空間
602 底部基板/インターポーザ組立体
604 第1の集積回路ダイ
606 上部基板/インターポーザ組立体
608a 導電性ポスト
608b 導電性ポスト
608c 導電性ポスト
608d 導電性ポスト
610a 導電性コンタクト
610b 導電性コンタクト
610c 導電性コンタクト
610d 導電性コンタクト
612 誘電体
614a はんだボール
614b はんだボール
614c はんだボール
614d はんだボール
616a 導電性コンタクト
616b 導電性コンタクト
616c 導電性コンタクト
616d 導電性コンタクト
618 内部空間
620 第2の集積回路ダイ
622 モールドまたはエポキシフラックス
702 コア材料、基板/インターポーザコア
704 上部金属層
704a 導電性コンタクト
704b 導電性コンタクト
704c 導電性コンタクト
704d 導電性コンタクト
704e 導電性コンタクト
704f 導電性コンタクト
706 底部金属層
706a 導電性コンタクト
706b 導電性コンタクト
706c 導電性コンタクト
706d 導電性コンタクト
706e 導電性コンタクト
706f 導電性コンタクト
708a ビア
708d ビア
708e ビア
710 基板材料、はんだレジスト
712 基板材料、はんだレジスト
714 基板/インターポーザ組立体
716 誘電体被覆
718a 開口
718b 開口
718c 中心開口
718d 開口
718e 開口
720 裏面マスク
722a 導電性ポスト
722b 導電性ポスト
722c 導電性ポスト
722d 導電性ポスト
802 シード層
804 裏面マスク
806 マスク
808a 底部部分
808b 底部部分
808c 底部部分
808d 底部部分
h1 高さ
h2 高さ
h3 組み合わせた高さ
Claims (30)
- 第1の表面および第2の表面を備える第1の基板と、
前記第1の基板の前記第1の表面上の複数の導電性コンタクトと、
前記第1の基板の前記第1の表面上にあり、複数の開口を有する誘電体と、
前記導電性コンタクトのうちの少なくとも一部に結合された複数の導電性ポストと
を備え、前記誘電体が前記複数の導電性ポストを少なくとも部分的に取り囲む、デバイス。 - 前記第1の基板が第1のインターポーザを備える、請求項1に記載のデバイス。
- 前記誘電体がフォトイメージャブル誘電体(PID)を含む、請求項1に記載のデバイス。
- 前記導電性ポストが銅ポストを備える、請求項1に記載のデバイス。
- 前記導電性ポストにそれぞれ結合された複数の導電性パッドをさらに備える、請求項1に記載のデバイス。
- 前記導電性パッドが銅パッドを備える、請求項5に記載のデバイス。
- 第1の表面および第2の表面を有する第2の基板と、
前記第2の基板の前記第1の表面上の複数の導電性コンタクトと
をさらに備える、請求項1に記載のデバイス。 - 前記第2の基板が第2のインターポーザを備える、請求項7に記載のデバイス。
- 前記導電性ポストが、前記導電性コンタクトのうちの少なくとも一部に電気的に結合される、請求項7に記載のデバイス。
- 前記導電性ポストと前記導電性コンタクトのうちの前記少なくとも一部との間にそれぞれ結合された、複数のはんだボールをさらに備える、請求項9に記載のデバイス。
- 前記誘電体内の開口内に集積回路ダイをさらに備える、請求項7に記載のデバイス。
- 前記集積回路ダイが、前記第2の基板の前記第1の表面上に配設される、請求項11に記載のデバイス。
- 前記第1の基板の前記第2の表面上に配設された第2の集積回路ダイをさらに備える、請求項12に記載のデバイス。
- 前記第1の基板の前記第2の表面および前記第2の集積回路ダイ上にモールドをさらに備える、請求項13に記載のデバイス。
- 第1の表面および第2の表面を有する第1の基板と、
前記第1の基板の前記第1の表面上の第1の複数の導電性コンタクトと、
第1の表面および第2の表面を有する第2の基板と、
前記第2の基板の前記第1の表面上の第2の複数の導電性コンタクトと、
前記第1の基板の前記第1の表面と前記第2の基板の前記第1の表面との間に配設された誘電体であって、複数の開口を有する、誘電体と、
前記誘電体内の前記開口のすべてではないが前記開口の一部内に配設された複数の導電性ポストであって、前記第1の基板の前記第1の表面上の前記第1の複数の導電性コンタクトのうちの少なくとも一部、および前記第2の基板の前記第1の表面上の前記第2の複数の導電性コンタクトのうちの少なくとも一部に電気的に結合された、導電性ポストと、
前記第2の基板の前記第1の表面上の、前記誘電体の前記開口のうち前記導電性ポストのうちの1つによって占有されていない1つの開口内に配設された、集積回路ダイと
を備える、集積回路パッケージ。 - 前記第1の基板が第1のインターポーザを備え、前記第2の基板が第2のインターポーザを備える、請求項15に記載の集積回路パッケージ。
- 前記誘電体がフォトイメージャブル誘電体(PID)を含む、請求項15に記載の集積回路パッケージ。
- 前記導電性ポストが銅ポストを備える、請求項15に記載の集積回路パッケージ。
- 前記導電性ポストにそれぞれ結合された複数の導電性パッドをさらに備える、請求項15に記載の集積回路パッケージ。
- 前記導電性パッドが銅パッドを備える、請求項19に記載の集積回路パッケージ。
- 前記導電性ポストと前記第2の基板の前記第1の表面上の前記第2の複数の導電性コンタクトのうちの前記少なくとも一部との間にそれぞれ結合された、複数のはんだボールをさらに備える、請求項15に記載の集積回路パッケージ。
- 前記第1の基板の前記第2の表面上に配設された第2の集積回路ダイをさらに備える、請求項15に記載の集積回路パッケージ。
- 前記第1の基板の前記第2の表面および前記第2の集積回路ダイ上にモールドをさらに備える、請求項22に記載の集積回路パッケージ。
- 第1の表面および第2の表面を有する基板を提供するステップと、
前記基板の少なくとも前記第1の表面上に複数の導電性コンタクトを形成するステップと、
前記基板の前記第1の表面上に誘電体を形成するステップと、
前記誘電体内に複数の開口を形成するステップと、
前記誘電体内の前記開口のすべてではないが前記開口の一部内に複数の導電性ポストを形成するステップと
を含む、デバイスを作製する方法。 - 前記基板がインターポーザを備える、請求項24に記載の方法。
- 前記誘電体内の前記開口のすべてではないが前記開口の一部内に複数の導電性ポストを形成するステップが、金属でめっきするステップを含む、請求項24に記載の方法。
- 前記金属が銅を含む、請求項26に記載の方法。
- 前記誘電体がフォトイメージャブル誘電体(PID)を含む、請求項24に記載の方法。
- 前記導電性ポスト上にそれぞれ複数の導電性パッドを形成するステップをさらに含む、請求項24に記載の方法。
- 前記導電性パッドがそれぞれ、前記導電性ポストの一体延長部分として形成される、請求項29に記載の方法。
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US14/859,318 US9768108B2 (en) | 2015-02-20 | 2015-09-20 | Conductive post protection for integrated circuit packages |
PCT/US2016/018504 WO2016134165A1 (en) | 2015-02-20 | 2016-02-18 | Conductive post protection for integrated circuit packages |
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