CN107251217B - 用于集成电路封装的导电柱保护 - Google Patents
用于集成电路封装的导电柱保护 Download PDFInfo
- Publication number
- CN107251217B CN107251217B CN201680010443.6A CN201680010443A CN107251217B CN 107251217 B CN107251217 B CN 107251217B CN 201680010443 A CN201680010443 A CN 201680010443A CN 107251217 B CN107251217 B CN 107251217B
- Authority
- CN
- China
- Prior art keywords
- conductive
- substrate
- dielectric
- pillars
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/10—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L25/105—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1017—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support
- H01L2225/1023—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/10—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers
- H01L2225/1005—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10
- H01L2225/1011—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices having separate containers the devices being integrated devices of class H10 the containers being in a stacked arrangement
- H01L2225/1047—Details of electrical connections between containers
- H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Combinations Of Printed Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562118886P | 2015-02-20 | 2015-02-20 | |
| US62/118,886 | 2015-02-20 | ||
| US14/859,318 US9768108B2 (en) | 2015-02-20 | 2015-09-20 | Conductive post protection for integrated circuit packages |
| US14/859,318 | 2015-09-20 | ||
| PCT/US2016/018504 WO2016134165A1 (en) | 2015-02-20 | 2016-02-18 | Conductive post protection for integrated circuit packages |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107251217A CN107251217A (zh) | 2017-10-13 |
| CN107251217B true CN107251217B (zh) | 2021-03-12 |
Family
ID=55442905
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201680010443.6A Expired - Fee Related CN107251217B (zh) | 2015-02-20 | 2016-02-18 | 用于集成电路封装的导电柱保护 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US9768108B2 (enExample) |
| EP (1) | EP3259776A1 (enExample) |
| JP (1) | JP6789228B2 (enExample) |
| KR (1) | KR102469282B1 (enExample) |
| CN (1) | CN107251217B (enExample) |
| BR (1) | BR112017017746A2 (enExample) |
| SG (1) | SG11201705672XA (enExample) |
| WO (1) | WO2016134165A1 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102397905B1 (ko) | 2017-12-27 | 2022-05-13 | 삼성전자주식회사 | 인터포저 기판 및 반도체 패키지 |
| US11791276B2 (en) * | 2021-04-08 | 2023-10-17 | Qualcomm Incorporated | Package comprising passive component between substrates for improved power distribution network (PDN) performance |
| WO2023135720A1 (ja) * | 2022-01-14 | 2023-07-20 | キヤノン株式会社 | モジュールおよび機器 |
| US20250323136A1 (en) * | 2024-04-12 | 2025-10-16 | Qualcomm Incorporated | Integrated circuit (ic) package including two substrates and vertical interconnects coupling the two substrates, the vertical interconnects comprising a metal ball and metal pin combination to address an increased distance between substrates |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104051389A (zh) * | 2013-03-12 | 2014-09-17 | 台湾积体电路制造股份有限公司 | 具有焊盘连接件上通孔的叠层封装件 |
Family Cites Families (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000208698A (ja) * | 1999-01-18 | 2000-07-28 | Toshiba Corp | 半導体装置 |
| JP2003347501A (ja) * | 2002-05-23 | 2003-12-05 | Hitachi Cable Ltd | 半導体モジュール及びそれに用いる配線板、ならびに半導体モジュールの製造方法及び配線板の製造方法 |
| JP3973624B2 (ja) * | 2003-12-24 | 2007-09-12 | 富士通株式会社 | 高周波デバイス |
| JP4396839B2 (ja) * | 2004-08-11 | 2010-01-13 | 日本電気株式会社 | キャビティ構造プリント配線板とその製造方法及び実装構造 |
| JP4551321B2 (ja) * | 2005-07-21 | 2010-09-29 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
| JP2007053235A (ja) * | 2005-08-18 | 2007-03-01 | Matsushita Electric Ind Co Ltd | 基台及び半導体デバイス |
| JP2007123524A (ja) * | 2005-10-27 | 2007-05-17 | Shinko Electric Ind Co Ltd | 電子部品内蔵基板 |
| US7632708B2 (en) | 2005-12-27 | 2009-12-15 | Tessera, Inc. | Microelectronic component with photo-imageable substrate |
| JP2007194436A (ja) * | 2006-01-19 | 2007-08-02 | Elpida Memory Inc | 半導体パッケージ、導電性ポスト付き基板、積層型半導体装置、半導体パッケージの製造方法及び積層型半導体装置の製造方法 |
| JP2009099750A (ja) * | 2007-10-17 | 2009-05-07 | Powertech Technology Inc | 半導体パッケージ |
| JP5185062B2 (ja) * | 2008-10-21 | 2013-04-17 | パナソニック株式会社 | 積層型半導体装置及び電子機器 |
| US8623753B1 (en) * | 2009-05-28 | 2014-01-07 | Amkor Technology, Inc. | Stackable protruding via package and method |
| JP2011095705A (ja) * | 2009-09-30 | 2011-05-12 | Fujifilm Corp | 感光性組成物、感光性ソルダーレジスト組成物及び感光性ソルダーレジストフィルム、並びに、永久パターン、その形成方法及びプリント基板 |
| US8169065B2 (en) * | 2009-12-22 | 2012-05-01 | Epic Technologies, Inc. | Stackable circuit structures and methods of fabrication thereof |
| US8531021B2 (en) | 2011-01-27 | 2013-09-10 | Unimicron Technology Corporation | Package stack device and fabrication method thereof |
| US8476770B2 (en) | 2011-07-07 | 2013-07-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and methods for forming through vias |
| US8637992B2 (en) | 2011-11-30 | 2014-01-28 | Invensas Corporation | Flip chip package for DRAM with two underfill materials |
| US9362143B2 (en) | 2012-05-14 | 2016-06-07 | Micron Technology, Inc. | Methods for forming semiconductor device packages with photoimageable dielectric adhesive material, and related semiconductor device packages |
| CN103632988B (zh) * | 2012-08-28 | 2016-10-19 | 宏启胜精密电子(秦皇岛)有限公司 | 层叠封装结构及其制作方法 |
| CN103681365B (zh) * | 2012-08-31 | 2016-08-10 | 宏启胜精密电子(秦皇岛)有限公司 | 层叠封装结构及其制作方法 |
| CN103681359A (zh) * | 2012-09-19 | 2014-03-26 | 宏启胜精密电子(秦皇岛)有限公司 | 层叠封装结构及其制作方法 |
| US9368438B2 (en) | 2012-12-28 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package (PoP) bonding structures |
| US8946901B2 (en) | 2013-01-22 | 2015-02-03 | Invensas Corporation | Microelectronic package and method of manufacture thereof |
| US9378982B2 (en) | 2013-01-31 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package |
| US9167710B2 (en) | 2013-08-07 | 2015-10-20 | Invensas Corporation | Embedded packaging with preformed vias |
-
2015
- 2015-09-20 US US14/859,318 patent/US9768108B2/en active Active
-
2016
- 2016-02-18 SG SG11201705672XA patent/SG11201705672XA/en unknown
- 2016-02-18 CN CN201680010443.6A patent/CN107251217B/zh not_active Expired - Fee Related
- 2016-02-18 KR KR1020177022975A patent/KR102469282B1/ko active Active
- 2016-02-18 JP JP2017543343A patent/JP6789228B2/ja active Active
- 2016-02-18 EP EP16706746.1A patent/EP3259776A1/en not_active Withdrawn
- 2016-02-18 BR BR112017017746-3A patent/BR112017017746A2/en not_active Application Discontinuation
- 2016-02-18 WO PCT/US2016/018504 patent/WO2016134165A1/en not_active Ceased
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104051389A (zh) * | 2013-03-12 | 2014-09-17 | 台湾积体电路制造股份有限公司 | 具有焊盘连接件上通孔的叠层封装件 |
Also Published As
| Publication number | Publication date |
|---|---|
| BR112017017746A2 (en) | 2018-04-03 |
| SG11201705672XA (en) | 2017-09-28 |
| KR20170113581A (ko) | 2017-10-12 |
| EP3259776A1 (en) | 2017-12-27 |
| KR102469282B1 (ko) | 2022-11-18 |
| JP2018507556A (ja) | 2018-03-15 |
| US9768108B2 (en) | 2017-09-19 |
| US20160247754A1 (en) | 2016-08-25 |
| CN107251217A (zh) | 2017-10-13 |
| WO2016134165A1 (en) | 2016-08-25 |
| JP6789228B2 (ja) | 2020-11-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20230354523A1 (en) | Stackable via package and method | |
| US11152296B2 (en) | Semiconductor package and manufacturing method thereof | |
| US10257942B1 (en) | Stackable variable height via package and method | |
| KR100800478B1 (ko) | 적층형 반도체 패키지 및 그의 제조방법 | |
| US7825514B2 (en) | Substrate for semiconductor device, resin-sealed semiconductor device, method for manufacturing said substrate for semiconductor device and method for manufacturing said resin-sealed semiconductor device | |
| KR20070101157A (ko) | 솔더 접속부의 형성 방법, 배선 기판의 형성 방법 및반도체 장치의 제조 방법 | |
| US20110260334A1 (en) | Semiconductor device | |
| CN107251217B (zh) | 用于集成电路封装的导电柱保护 | |
| TWI581396B (zh) | 立體堆疊式封裝結構及其製作方法 | |
| JP2017038075A (ja) | エリアアレイユニットコネクタを備えるスタック可能モールド超小型電子パッケージ | |
| JP5905104B2 (ja) | はんだ付け緩和方法およびそれを使用した半導体デバイス | |
| US20090321953A1 (en) | Circuit substrate having circuit wire formed of conductive polarization particles, method of manufacturing the circuit substrate and semiconductor package having the circuit wire | |
| KR20140007659A (ko) | 멀티-칩 패키지 및 그의 제조 방법 | |
| TWI397157B (zh) | 具微機電元件之封裝結構及其製法 | |
| WO2006097779A1 (en) | Substrate, electronic component, electronic configuration and methods of producing the same | |
| HK1242841A1 (en) | Conductive post protection for integrated circuit packages | |
| US7732934B2 (en) | Semiconductor device having conductive adhesive layer and method of fabricating the same | |
| HK1242841B (zh) | 用於集成电路封装的导电柱保护 | |
| CN108028243B (zh) | 使用空腔结构的晶片级封装(wlp)球型支撑 | |
| KR20130015683A (ko) | 반도체 장치 및 이의 제조 방법 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| REG | Reference to a national code |
Ref country code: HK Ref legal event code: DE Ref document number: 1242841 Country of ref document: HK |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20210312 Termination date: 20220218 |