JP2017509154A5 - - Google Patents
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- Publication number
- JP2017509154A5 JP2017509154A5 JP2016554867A JP2016554867A JP2017509154A5 JP 2017509154 A5 JP2017509154 A5 JP 2017509154A5 JP 2016554867 A JP2016554867 A JP 2016554867A JP 2016554867 A JP2016554867 A JP 2016554867A JP 2017509154 A5 JP2017509154 A5 JP 2017509154A5
- Authority
- JP
- Japan
- Prior art keywords
- polymer layer
- dielectric polymer
- pads
- vias
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/196,481 | 2014-03-04 | ||
| US14/196,481 US9596768B2 (en) | 2014-03-04 | 2014-03-04 | Substrate with conductive vias |
| PCT/US2015/017802 WO2015134279A1 (en) | 2014-03-04 | 2015-02-26 | Substrate with conductive vias |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018127434A Division JP2018152616A (ja) | 2014-03-04 | 2018-07-04 | 導電性ビアを備える基板 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2017509154A JP2017509154A (ja) | 2017-03-30 |
| JP2017509154A5 true JP2017509154A5 (enExample) | 2017-07-06 |
Family
ID=52630528
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016554867A Pending JP2017509154A (ja) | 2014-03-04 | 2015-02-26 | 導電性ビアを備える基板 |
| JP2018127434A Pending JP2018152616A (ja) | 2014-03-04 | 2018-07-04 | 導電性ビアを備える基板 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2018127434A Pending JP2018152616A (ja) | 2014-03-04 | 2018-07-04 | 導電性ビアを備える基板 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US9596768B2 (enExample) |
| EP (1) | EP3114706A1 (enExample) |
| JP (2) | JP2017509154A (enExample) |
| CN (1) | CN106068561A (enExample) |
| WO (1) | WO2015134279A1 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9812359B2 (en) * | 2015-06-08 | 2017-11-07 | Globalfoundries Inc. | Thru-silicon-via structures |
| MY191331A (en) * | 2016-12-30 | 2022-06-16 | Intel Corp | Substrate with gradiated dielectric for reducing impedance mismatch |
| CN111010797A (zh) * | 2018-10-08 | 2020-04-14 | 中兴通讯股份有限公司 | 电路板、设备及过孔形成方法 |
| CN109378296B (zh) * | 2018-10-11 | 2020-12-01 | 深圳市修颐投资发展合伙企业（有限合伙） | 电子零件与基板互连方法 |
| MY202414A (en) * | 2018-11-28 | 2024-04-27 | Intel Corp | Embedded reference layers fo semiconductor package substrates |
| US11282777B2 (en) * | 2019-12-31 | 2022-03-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method of manufacturing the same |
| KR20220054034A (ko) * | 2020-10-23 | 2022-05-02 | 삼성전자주식회사 | 디스플레이 모듈 및 그 제조 방법 |
| US20230395445A1 (en) * | 2022-06-06 | 2023-12-07 | Intel Corporation | Glass core architectures with dielectric buffer layer between glass core and metal vias and pads |
| CN114942539A (zh) * | 2022-06-10 | 2022-08-26 | 昆山弗莱吉电子科技有限公司 | 用于液晶显示器的玻璃基板及其生产工艺 |
| US12431410B2 (en) * | 2023-01-06 | 2025-09-30 | Nanya Technology Corporation | Semiconductor device with polymer liner and method for fabricating the same |
| US12087623B1 (en) * | 2024-01-25 | 2024-09-10 | Yield Engineering Systems, Inc. | Dielectric liners on through glass vias |
Family Cites Families (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63157439A (ja) * | 1986-12-20 | 1988-06-30 | Fujitsu Ltd | スル−ホ−ル内の多層配線構造 |
| EP1419526A2 (en) * | 2001-08-24 | 2004-05-19 | MCNC Research and Development Institute | Through-via vertical interconnects, through-via heat sinks and associated fabrication methods |
| EP1465246B1 (en) | 2003-04-03 | 2013-12-18 | Imec | Method for producing electrical through hole interconnects |
| JP2005026405A (ja) | 2003-07-01 | 2005-01-27 | Sharp Corp | 貫通電極構造およびその製造方法、半導体チップならびにマルチチップ半導体装置 |
| US7345350B2 (en) | 2003-09-23 | 2008-03-18 | Micron Technology, Inc. | Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias |
| JP2005332936A (ja) | 2004-05-19 | 2005-12-02 | Canon Inc | 半導体装置および半導体装置の製造方法 |
| KR100858075B1 (ko) | 2004-07-06 | 2008-09-11 | 도쿄엘렉트론가부시키가이샤 | 인터포저 |
| JP2006024653A (ja) * | 2004-07-06 | 2006-01-26 | Tokyo Electron Ltd | 貫通基板および貫通基板の製造方法 |
| US7129567B2 (en) | 2004-08-31 | 2006-10-31 | Micron Technology, Inc. | Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements |
| US7772116B2 (en) | 2005-09-01 | 2010-08-10 | Micron Technology, Inc. | Methods of forming blind wafer interconnects |
| US7989915B2 (en) | 2006-07-11 | 2011-08-02 | Teledyne Licensing, Llc | Vertical electrical device |
| JP2008053568A (ja) * | 2006-08-25 | 2008-03-06 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
| US8115292B2 (en) | 2008-10-23 | 2012-02-14 | United Test And Assembly Center Ltd. | Interposer for semiconductor package |
| TWI459520B (zh) | 2011-01-31 | 2014-11-01 | 精材科技股份有限公司 | 轉接板及其形成方法 |
| US8816505B2 (en) | 2011-07-29 | 2014-08-26 | Tessera, Inc. | Low stress vias |
| KR20130057314A (ko) * | 2011-11-23 | 2013-05-31 | 삼성전기주식회사 | 인쇄회로기판 및 인쇄회로기판 제조 방법 |
| KR101916225B1 (ko) | 2012-04-09 | 2018-11-07 | 삼성전자 주식회사 | Ｔｓｖ를 구비한 반도체 칩 및 그 반도체 칩 제조방법 |
-
2014
- 2014-03-04 US US14/196,481 patent/US9596768B2/en not_active Expired - Fee Related
-
2015
- 2015-02-26 WO PCT/US2015/017802 patent/WO2015134279A1/en not_active Ceased
- 2015-02-26 JP JP2016554867A patent/JP2017509154A/ja active Pending
- 2015-02-26 EP EP15708673.7A patent/EP3114706A1/en not_active Withdrawn
- 2015-02-26 CN CN201580011643.9A patent/CN106068561A/zh active Pending
-
2018
- 2018-07-04 JP JP2018127434A patent/JP2018152616A/ja active Pending
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