CN106068561A - 具有导电通孔的基板 - Google Patents

具有导电通孔的基板 Download PDF

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Publication number
CN106068561A
CN106068561A CN201580011643.9A CN201580011643A CN106068561A CN 106068561 A CN106068561 A CN 106068561A CN 201580011643 A CN201580011643 A CN 201580011643A CN 106068561 A CN106068561 A CN 106068561A
Authority
CN
China
Prior art keywords
metal
substrate
dielectric polymer
polymer layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201580011643.9A
Other languages
English (en)
Chinese (zh)
Inventor
H·B·蔚
D·W·金
J·S·李
S·顾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN106068561A publication Critical patent/CN106068561A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0265—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the sidewall insulation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H10W20/2128—Coaxial through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
CN201580011643.9A 2014-03-04 2015-02-26 具有导电通孔的基板 Pending CN106068561A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/196,481 2014-03-04
US14/196,481 US9596768B2 (en) 2014-03-04 2014-03-04 Substrate with conductive vias
PCT/US2015/017802 WO2015134279A1 (en) 2014-03-04 2015-02-26 Substrate with conductive vias

Publications (1)

Publication Number Publication Date
CN106068561A true CN106068561A (zh) 2016-11-02

Family

ID=52630528

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201580011643.9A Pending CN106068561A (zh) 2014-03-04 2015-02-26 具有导电通孔的基板

Country Status (5)

Country Link
US (1) US9596768B2 (enExample)
EP (1) EP3114706A1 (enExample)
JP (2) JP2017509154A (enExample)
CN (1) CN106068561A (enExample)
WO (1) WO2015134279A1 (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109378296A (zh) * 2018-10-11 2019-02-22 深圳市修颐投资发展合伙企业（有限合伙） 电子零件与基板互连方法
CN114942539A (zh) * 2022-06-10 2022-08-26 昆山弗莱吉电子科技有限公司 用于液晶显示器的玻璃基板及其生产工艺
US20240234249A1 (en) * 2023-01-06 2024-07-11 Nanya Technology Corporation Semiconductor device with polymer liner and method for fabricating the same

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* Cited by examiner, † Cited by third party
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US9812359B2 (en) * 2015-06-08 2017-11-07 Globalfoundries Inc. Thru-silicon-via structures
MY191331A (en) * 2016-12-30 2022-06-16 Intel Corp Substrate with gradiated dielectric for reducing impedance mismatch
CN111010797A (zh) * 2018-10-08 2020-04-14 中兴通讯股份有限公司 电路板、设备及过孔形成方法
MY202414A (en) 2018-11-28 2024-04-27 Intel Corp Embedded reference layers fo semiconductor package substrates
IT201900006736A1 (it) * 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
US11282777B2 (en) * 2019-12-31 2022-03-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
KR102904020B1 (ko) * 2020-10-23 2025-12-26 삼성전자주식회사 디스플레이 모듈 및 그 제조 방법
US20230395445A1 (en) * 2022-06-06 2023-12-07 Intel Corporation Glass core architectures with dielectric buffer layer between glass core and metal vias and pads
US20250140646A1 (en) * 2023-10-31 2025-05-01 Nanya Technology Corporation Semiconductor device with polymer liner and method for fabricating the same
US12087623B1 (en) * 2024-01-25 2024-09-10 Yield Engineering Systems, Inc. Dielectric liners on through glass vias

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US20080122031A1 (en) * 2006-07-11 2008-05-29 Rockwell Scientific Licensing, Llc Vertical electrical device
US20120193811A1 (en) * 2011-01-31 2012-08-02 Yang ming-kun Interposer and method for forming the same
US20130126224A1 (en) * 2011-11-23 2013-05-23 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same

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JPS63157439A (ja) * 1986-12-20 1988-06-30 Fujitsu Ltd スル−ホ−ル内の多層配線構造
EP1419526A2 (en) * 2001-08-24 2004-05-19 MCNC Research and Development Institute Through-via vertical interconnects, through-via heat sinks and associated fabrication methods
EP2704187B1 (en) 2003-04-03 2015-08-19 Imec METHOD FOR PRODUCING ELECTRICAL THROUGH HOLE INTERCONNECTS AND corresponding DEVICE
JP2005026405A (ja) 2003-07-01 2005-01-27 Sharp Corp 貫通電極構造およびその製造方法、半導体チップならびにマルチチップ半導体装置
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
JP2005332936A (ja) 2004-05-19 2005-12-02 Canon Inc 半導体装置および半導体装置の製造方法
WO2006004128A1 (ja) 2004-07-06 2006-01-12 Tokyo Electron Limited 貫通基板およびインターポーザ、ならびに貫通基板の製造方法
JP2006024653A (ja) * 2004-07-06 2006-01-26 Tokyo Electron Ltd 貫通基板および貫通基板の製造方法
US7129567B2 (en) 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
US7772116B2 (en) 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
JP2008053568A (ja) * 2006-08-25 2008-03-06 Nec Electronics Corp 半導体装置および半導体装置の製造方法
US8115292B2 (en) 2008-10-23 2012-02-14 United Test And Assembly Center Ltd. Interposer for semiconductor package
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080122031A1 (en) * 2006-07-11 2008-05-29 Rockwell Scientific Licensing, Llc Vertical electrical device
US20120193811A1 (en) * 2011-01-31 2012-08-02 Yang ming-kun Interposer and method for forming the same
US20130126224A1 (en) * 2011-11-23 2013-05-23 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109378296A (zh) * 2018-10-11 2019-02-22 深圳市修颐投资发展合伙企业（有限合伙） 电子零件与基板互连方法
CN114942539A (zh) * 2022-06-10 2022-08-26 昆山弗莱吉电子科技有限公司 用于液晶显示器的玻璃基板及其生产工艺
US20240234249A1 (en) * 2023-01-06 2024-07-11 Nanya Technology Corporation Semiconductor device with polymer liner and method for fabricating the same
US12431410B2 (en) * 2023-01-06 2025-09-30 Nanya Technology Corporation Semiconductor device with polymer liner and method for fabricating the same

Also Published As

Publication number Publication date
JP2017509154A (ja) 2017-03-30
EP3114706A1 (en) 2017-01-11
WO2015134279A1 (en) 2015-09-11
US20150257282A1 (en) 2015-09-10
US9596768B2 (en) 2017-03-14
JP2018152616A (ja) 2018-09-27

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C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
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Application publication date: 20161102