JP2017509154A - 導電性ビアを備える基板 - Google Patents

導電性ビアを備える基板 Download PDF

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Publication number
JP2017509154A
JP2017509154A JP2016554867A JP2016554867A JP2017509154A JP 2017509154 A JP2017509154 A JP 2017509154A JP 2016554867 A JP2016554867 A JP 2016554867A JP 2016554867 A JP2016554867 A JP 2016554867A JP 2017509154 A JP2017509154 A JP 2017509154A
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JP
Japan
Prior art keywords
metal
substrate
polymer layer
dielectric polymer
layer
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Pending
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JP2016554867A
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English (en)
Japanese (ja)
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JP2017509154A5 (enExample
Inventor
ホン・ボク・ウィ
ドン・ウク・キム
ジェ・シク・イ
シーチュン・グ
Original Assignee
クアルコム，インコーポレイテッド
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Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2017509154A publication Critical patent/JP2017509154A/ja
Publication of JP2017509154A5 publication Critical patent/JP2017509154A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/426—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates without metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP2016554867A 2014-03-04 2015-02-26 導電性ビアを備える基板 Pending JP2017509154A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/196,481 2014-03-04
US14/196,481 US9596768B2 (en) 2014-03-04 2014-03-04 Substrate with conductive vias
PCT/US2015/017802 WO2015134279A1 (en) 2014-03-04 2015-02-26 Substrate with conductive vias

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2018127434A Division JP2018152616A (ja) 2014-03-04 2018-07-04 導電性ビアを備える基板

Publications (2)

Publication Number Publication Date
JP2017509154A true JP2017509154A (ja) 2017-03-30
JP2017509154A5 JP2017509154A5 (enExample) 2017-07-06

Family

ID=52630528

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2016554867A Pending JP2017509154A (ja) 2014-03-04 2015-02-26 導電性ビアを備える基板
JP2018127434A Pending JP2018152616A (ja) 2014-03-04 2018-07-04 導電性ビアを備える基板

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2018127434A Pending JP2018152616A (ja) 2014-03-04 2018-07-04 導電性ビアを備える基板

Country Status (5)

Country Link
US (1) US9596768B2 (enExample)
EP (1) EP3114706A1 (enExample)
JP (2) JP2017509154A (enExample)
CN (1) CN106068561A (enExample)
WO (1) WO2015134279A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240234249A1 (en) * 2023-01-06 2024-07-11 Nanya Technology Corporation Semiconductor device with polymer liner and method for fabricating the same

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US9812359B2 (en) * 2015-06-08 2017-11-07 Globalfoundries Inc. Thru-silicon-via structures
MY191331A (en) * 2016-12-30 2022-06-16 Intel Corp Substrate with gradiated dielectric for reducing impedance mismatch
CN111010797A (zh) * 2018-10-08 2020-04-14 中兴通讯股份有限公司 电路板、设备及过孔形成方法
CN109378296B (zh) * 2018-10-11 2020-12-01 深圳市修颐投资发展合伙企业（有限合伙） 电子零件与基板互连方法
MY202414A (en) 2018-11-28 2024-04-27 Intel Corp Embedded reference layers fo semiconductor package substrates
US11282777B2 (en) * 2019-12-31 2022-03-22 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
KR20220054034A (ko) * 2020-10-23 2022-05-02 삼성전자주식회사 디스플레이 모듈 및 그 제조 방법
US20230395445A1 (en) * 2022-06-06 2023-12-07 Intel Corporation Glass core architectures with dielectric buffer layer between glass core and metal vias and pads
CN114942539A (zh) * 2022-06-10 2022-08-26 昆山弗莱吉电子科技有限公司 用于液晶显示器的玻璃基板及其生产工艺
US12087623B1 (en) * 2024-01-25 2024-09-10 Yield Engineering Systems, Inc. Dielectric liners on through glass vias

Citations (7)

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JP2005501413A (ja) * 2001-08-24 2005-01-13 エムシーエヌシー リサーチ アンド デベロップメント インスティテュート 貫通ビア垂直配線、貫通ビア型ヒートシンク及び関連する形成方法
JP2005332936A (ja) * 2004-05-19 2005-12-02 Canon Inc 半導体装置および半導体装置の製造方法
JP2006024653A (ja) * 2004-07-06 2006-01-26 Tokyo Electron Ltd 貫通基板および貫通基板の製造方法
US20080122031A1 (en) * 2006-07-11 2008-05-29 Rockwell Scientific Licensing, Llc Vertical electrical device
JP2012160734A (ja) * 2011-01-31 2012-08-23 Xitec Inc インターポーザ及びその形成方法
US20130026645A1 (en) * 2011-07-29 2013-01-31 Tessera, Inc. Low stress vias
US20130126224A1 (en) * 2011-11-23 2013-05-23 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same

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JPS63157439A (ja) * 1986-12-20 1988-06-30 Fujitsu Ltd スル−ホ−ル内の多層配線構造
EP1465246B1 (en) 2003-04-03 2013-12-18 Imec Method for producing electrical through hole interconnects
JP2005026405A (ja) 2003-07-01 2005-01-27 Sharp Corp 貫通電極構造およびその製造方法、半導体チップならびにマルチチップ半導体装置
US7345350B2 (en) 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
KR100858075B1 (ko) 2004-07-06 2008-09-11 도쿄엘렉트론가부시키가이샤 인터포저
US7129567B2 (en) 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
US7772116B2 (en) 2005-09-01 2010-08-10 Micron Technology, Inc. Methods of forming blind wafer interconnects
JP2008053568A (ja) * 2006-08-25 2008-03-06 Nec Electronics Corp 半導体装置および半導体装置の製造方法
US8115292B2 (en) 2008-10-23 2012-02-14 United Test And Assembly Center Ltd. Interposer for semiconductor package
KR101916225B1 (ko) 2012-04-09 2018-11-07 삼성전자 주식회사 Ｔｓｖ를 구비한 반도체 칩 및 그 반도체 칩 제조방법

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005501413A (ja) * 2001-08-24 2005-01-13 エムシーエヌシー リサーチ アンド デベロップメント インスティテュート 貫通ビア垂直配線、貫通ビア型ヒートシンク及び関連する形成方法
JP2005332936A (ja) * 2004-05-19 2005-12-02 Canon Inc 半導体装置および半導体装置の製造方法
JP2006024653A (ja) * 2004-07-06 2006-01-26 Tokyo Electron Ltd 貫通基板および貫通基板の製造方法
US20080122031A1 (en) * 2006-07-11 2008-05-29 Rockwell Scientific Licensing, Llc Vertical electrical device
JP2012160734A (ja) * 2011-01-31 2012-08-23 Xitec Inc インターポーザ及びその形成方法
US20130026645A1 (en) * 2011-07-29 2013-01-31 Tessera, Inc. Low stress vias
US20130126224A1 (en) * 2011-11-23 2013-05-23 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240234249A1 (en) * 2023-01-06 2024-07-11 Nanya Technology Corporation Semiconductor device with polymer liner and method for fabricating the same
US12431410B2 (en) * 2023-01-06 2025-09-30 Nanya Technology Corporation Semiconductor device with polymer liner and method for fabricating the same

Also Published As

Publication number Publication date
WO2015134279A1 (en) 2015-09-11
US9596768B2 (en) 2017-03-14
JP2018152616A (ja) 2018-09-27
EP3114706A1 (en) 2017-01-11
CN106068561A (zh) 2016-11-02
US20150257282A1 (en) 2015-09-10

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