JP2016514367A5 - - Google Patents

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Publication number
JP2016514367A5
JP2016514367A5 JP2015560255A JP2015560255A JP2016514367A5 JP 2016514367 A5 JP2016514367 A5 JP 2016514367A5 JP 2015560255 A JP2015560255 A JP 2015560255A JP 2015560255 A JP2015560255 A JP 2015560255A JP 2016514367 A5 JP2016514367 A5 JP 2016514367A5
Authority
JP
Japan
Prior art keywords
substrate
traces
test pad
resist layer
solder resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2015560255A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016514367A (ja
Filing date
Publication date
Priority claimed from US13/783,168 external-priority patent/US9370097B2/en
Application filed filed Critical
Publication of JP2016514367A publication Critical patent/JP2016514367A/ja
Publication of JP2016514367A5 publication Critical patent/JP2016514367A5/ja
Pending legal-status Critical Current

Links

JP2015560255A 2013-03-01 2014-02-25 ファインピッチトレース上にテスト用パッドを有するパッケージ基板 Pending JP2016514367A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/783,168 US9370097B2 (en) 2013-03-01 2013-03-01 Package substrate with testing pads on fine pitch traces
US13/783,168 2013-03-01
PCT/US2014/018372 WO2014134059A2 (en) 2013-03-01 2014-02-25 Package substrate with testing pads on fine pitch traces

Publications (2)

Publication Number Publication Date
JP2016514367A JP2016514367A (ja) 2016-05-19
JP2016514367A5 true JP2016514367A5 (enExample) 2017-03-02

Family

ID=50342475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015560255A Pending JP2016514367A (ja) 2013-03-01 2014-02-25 ファインピッチトレース上にテスト用パッドを有するパッケージ基板

Country Status (6)

Country Link
US (1) US9370097B2 (enExample)
EP (1) EP2962535B1 (enExample)
JP (1) JP2016514367A (enExample)
KR (1) KR20150127630A (enExample)
CN (1) CN105009693B (enExample)
WO (1) WO2014134059A2 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106304627B (zh) * 2015-05-13 2019-10-29 上海和辉光电有限公司 一种测试焊盘结构及其制备方法
CN105611713A (zh) * 2015-12-22 2016-05-25 广东欧珀移动通信有限公司 Pcb板及其制作方法
US11637057B2 (en) * 2019-01-07 2023-04-25 Qualcomm Incorporated Uniform via pad structure having covered traces between partially covered pads
KR102442065B1 (ko) * 2020-11-06 2022-09-13 한국과학기술원 반도체 장치를 테스트하는 장치 및 그 방법

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6149471U (enExample) * 1984-09-03 1986-04-03
JPH1117057A (ja) * 1997-06-26 1999-01-22 Nec Corp 検査パッド付きｂｇａ型半導体装置
US20040012097A1 (en) 2002-07-17 2004-01-22 Chien-Wei Chang Structure and method for fine pitch flip chip substrate
US7307222B2 (en) * 2003-09-24 2007-12-11 Agilent Technologies, Inc. Printed circuit board test access point structures and method for making the same
JP2005294811A (ja) * 2004-03-10 2005-10-20 Matsushita Electric Ind Co Ltd 配線基板及びその製造方法
US20060103397A1 (en) * 2004-10-29 2006-05-18 Parker Kenneth P Method and apparatus for a twisting fixture probe for probing test access point structures
JP2008053548A (ja) 2006-08-25 2008-03-06 Sharp Corp 回路基板および電気回路の検査方法
JP4802155B2 (ja) * 2007-08-07 2011-10-26 京セラＳｌｃテクノロジー株式会社 配線基板
JP2010027798A (ja) 2008-07-17 2010-02-04 Toshiba Corp プリント配線板
US7569935B1 (en) * 2008-11-12 2009-08-04 Powertech Technology Inc. Pillar-to-pillar flip-chip assembly
JP2010206027A (ja) * 2009-03-04 2010-09-16 Renesas Electronics Corp Ｔｃｐ型半導体装置
US8586873B2 (en) * 2010-02-23 2013-11-19 Flextronics Ap, Llc Test point design for a high speed bus
US8053283B2 (en) 2010-03-25 2011-11-08 International Business Machines Corporation Die level integrated interconnect decal manufacturing method and apparatus
US8492197B2 (en) 2010-08-17 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method of forming vertically offset conductive pillars over first substrate aligned to vertically offset BOT interconnect sites formed over second substrate
US8669137B2 (en) 2011-04-01 2014-03-11 International Business Machines Corporation Copper post solder bumps on substrate
JP5789431B2 (ja) * 2011-06-30 2015-10-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US9269681B2 (en) * 2012-11-16 2016-02-23 Qualcomm Incorporated Surface finish on trace for a thermal compression flip chip (TCFC)

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